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ADMC326
–16–
REV. C
Table VI. ADC Auxiliary Channel Selection
MODECTRL (1)
ADCMUX1
MODECTRL (0)
ADCMUX0
Select
VAUX0
VAUX1
VAUX2
Calibration (V
REF
)
0
0
1
1
0
1
0
1
The single slope technique has been adapted on the ADMC326
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. Three of the
main inputs (V1, V2, and V3) are directly connected as high
impedance voltage inputs. The fourth channel has been configured
with a serially-connected 4-to-1 multiplexer. Table VI shows the
multiplexer input selection codes. One of these auxiliary multi-
plexed channels is used to calibrate the ramp against the internal
voltage reference (V
REF
).
VAUX0
V2L
VAUXL
PWMSYNC (CONVST)
CLK MODECTRL<7>
ADC
REGISTERS
V1L
V3L
V2
(CAP RESET)
12-BIT
ADC
TIMER
BLOCK
V
REF
COMP
ADC REGISTERS
ADC1
ADC2
ADC3
ADCAUX
MODECTRL<0..1>
EXTERNAL
CHARGING
CAP
V
C
ICONST
ICONST_TRIM<2:0>
VAUX1
VAUX2
COMP
COMP
COMP
V1
C
GND
4-TO-1
MUX
V3
Figure 11. ADC Overview
Comparing each ADC input to a reference ramp voltage, and tim-
ing the comparison of the two signals, performs the conversion
process. The actual conversion point is the time point intersec-
tion of the input voltage and the ramp voltage (V
C
) as shown in
Figure 12. This time is converted to counts by the 12-bit ADC
Timer Block and is stored in the ADC registers. The ramp volt-
age used to perform the conversion is generated by driving a
Table V. Fundamental Characteristics of PWM Generation Unit of ADMC326
16-BIT PWM TIMER
Parameter
Min
Typ
Max
Unit
Counter Resolution
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Dead Time Range
Programmable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (T
CRST
)
Gate Drive Chop Frequency Range
16
100
50
Bits
ns
ns
μ
s
ns
μ
s
ns
Hz
μ
s
MHz
0
100
100
0
100
100
150
0.05
0.02
12.5
5
fixed current into an off-chip capacitor, where the capacitor
voltage is
V
C
= (I/C)
×
t
Following reset,
V
C
= 0 at
t
= 0. This reset and the start of the
conversion process are initiated by the PWMSYNC pulse, as
shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT register and should be
programmed according to Figure 13 to ensure complete resetting.
In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of the
ADMC326 is software programmable. The software setting of the
magnitude of the ICONST current generator is accomplished by
selecting one of eight steps over an approximately 20% cur-
rent range.
V1
PWMSYNC
V
VIL
COMPARATOR
OUTPUT
t
T
CRST
T
PWM
–
T
CRST
t
VIL
V
C
V
CMAX
Figure 12. Analog Input Block Operation
The ADC system consists of four comparators and a single timer,
which may be clocked at either the DSP rate or half the DSP
rate depending on the setting of the ADCCNT bit (Bit 7) of the
MODECTRL register. When this bit is cleared, the timers count
at a slower rate of CLKIN. When this bit is set, they count at
CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,
and ADCAUX are the registers that capture the conversion times,
which are effectively the timer value when the associated com-
parator trips.