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參數(shù)資料
| 型號： | ADMC328 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號處理的的馬達(dá)控制器) |
| 中文描述： | 28 - ROM的鉛基于DSP的電機(jī)控制器（28腳含光盤，數(shù)字信號處理的的馬達(dá)控制器） |
| 文件頁數(shù)： | 10/36頁 |
| 文件大小： | 470K |
| 代理商： | ADMC328 |
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ADMC328
–10–
REV. A
SPORT 1 has independent framing for the receive and
transmit sections. Sections run in a frameless mode or
with frame synchronization signals internally or externally
generated. Frame synchronization signals are active high or
inverted, with either of two pulsewidths and timings.
SPORT 1 supports serial data word lengths from 3 bits to
16 bits and provides optional A-law and μ-law
companding according to IT U (formerly CCIT T ) rec-
ommendation G.711.
SPORT 1 receive and transmit sections can generate
unique interrupts on completing a data word transfer.
SPORT 1 can receive and transmit an entire circular
buffer of data with only one overhead cycle per data
word. An interrupt is generated after a data buffer trans-
fer.
SPORT 1 can be configured to have two external inter-
rupts (
IRQ0
and
IRQ1
), and the Flag In and Flag Out
signals. T he internally generated serial clock may still be
used in this configuration.
SPORT 1 has two data receive pins (DR1A and DR1B),
which are internally multiplexed onto the one DR1 port
of the SPORT 1. T he particular data receive pin selected
is determined by a bit in the MODECT RL register.
PIN FUNCTION DESCRIPTION
T he ADMC328 is available in an 28-lead SOIC package.
T able I describes the pins.
Table I. Pin List
Pin
Group
Name
#
of
Input/
Pins Output Function
RESET
SPORT 1
1
1
6
I
Processor reset input.
Serial port 1 pins (T FS1,
RFS1, DT 1, DR1A, DR1B,
SCL K 1).
Processor clock output.
External clock or quartz
Crystal connection point.
Digital I/O port pins.
Auxiliary PWM outputs.
PWM outputs.
PWM trip signal.
Analog Inputs.
Auxiliary analog input.
Current sense amplifier input.
ADC constant current
source.
Power supply.
Ground.
I/O
CLK OUT
1
CLK IN, X T AL
1
2
O
I,O
PIO0–PIO8
1
AUX 0–AUX 1
1
AH–CL
PWMTRIP
V1–V2
VAUX 0–VAUX 2
I
SENSE
ICONST
9
2
6
1
2
3
1
1
I/O
O
O
I
I
I
I
O
V
DD
GND
1
1
Notes:
1
Multiplexed pins, selectable individually through PIOSELECT and
PIODAT A1
.
INTERRUPT OVERVIEW
T he ADMC 328 can respond to 16 different interrupt
sources with minimal overhead, 5 of which are internal
DSP core interrupts and 11 are from the motor control pe-
ripherals. T he 5 DSP core interrupts are SPORT 1 receive
(or
IRQ0
) and transmit (or
IRQ1
), the internal timer, and
two software interrupts. T he motor control peripheral in-
terrupts are the 9 programmable I/Os and two from the
PWM (PWMSYNC pulse and
PWMTRIP
). All motor
control interrupts are multiplexed into the DSP core through
the peripheral
IRQ2
interrupt. T he interrupts are internally
prioritized and individually maskable. A detailed descrip-
tion of the entire interrupt system of the ADMC328 is
presented later, following a more detailed description of
each peripheral block.
Memory Map
T he ADMC 328 has two distinct memory types: program
memory and data memory. In general, program memory
contains user code and coefficients, while the data memory is
used to store variables and data during program execution.
Both program memory RAM and ROM are provided on the
ADMC328. Program memory RAM is arranged as one
contiguous 512
3
24-bit block, starting at address 0x0000.
Program memory ROM is a 4K
3
24-bit block located at
address 0x0800. Data memory is arranged as a 512
3
16-
bit block starting at address 0x3800. T he motor control
peripherals are memory mapped into a region of the data
memory space starting at 0x2000. T he complete program
and data memory maps are given in T ables II and III, re-
spectively.
Table II. Program Memory Map
Memory
Type
RAM
RAM
ROM
ROM
ROM
Address Range
0x0000–0x002F
0x0030–0x01FF
0x0800–0x0919
0x091A–0x17EF
0x017F0–0x17FF
Function
Interrupt Vector T able
User Program RAM
Reserved Program ROM
User Program ROM
Reserved Program ROM
Table III. Data Memory Map
Memory
Type
Address Range
Function
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x39FE
0x39FF–0x39FF
0x3A00–0x3BFF
0x3C00–0x3FFF
Memory Mapped Registers
Reserved
User Data Memory
Reserved for IRQFlag_Save
Reserved
DSP Memory Mapped
Registers
RAM
RAM
RAM
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| ADMC401-ADVEVALKIT | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:10-5 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADMC328TN | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TN-XXX-YY | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TR | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TR-XXX-YY | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328YN | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
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