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參數(shù)資料
| 型號： | ADM9690ARN |
| 英文描述： | IC-SM-SUPERVISORY CIRCUIT |
| 中文描述： | 集成電路釤監(jiān)控電路 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 78K |
| 代理商： | ADM9690ARN |
ADM9690
–5–
REV. 0
POWE R SUPPLY AND WAT CHDOG MONIT ORING
CIRCUIT
T he ADM9690 contains a power supply voltage monitoring
comparator and a watchdog timer monitor. Either V
MON
drop-
ping outside tolerance or the watchdog timer timing out results
in a reset sequence as discussed below. T wo reset outputs are
provided
. RESET(1)
and
RESET(2)
.
POWE R FAIL/POWE R-ON
RESET
When V
MON
falls below the reset threshold (4.4 V) both RESET
outputs are forced low immediately.
On power-up,
RESET(1)
will remain low for 50 milliseconds
after V
MON
rises above the reset threshold. T his provides a
power-on reset for the microprocessor.
RESET(2)
remains
active low for an additional 10 ms.
RESET(1)
is intended to
WATCHDOG
TRANSITION
DETECTOR
V
CC
V
MON
OSC SEL1
OSC SEL2
RESET(2)
TIMER
RESET(1)
TIMER
4.40V
ADM9690
RESET(1)
RESET(2)
WATCHDOG
INPUT (WDI)
GND
WATCHDOG
TIMEBASE
Figure 6. Functional Block Diagram
provide a power-on reset signal for the
μ
P while
RESET(2)
is
used to hold additional circuitry in a reset state until the
μ
P has
regained control following a power-up.
T he guaranteed minimum and maximum thresholds for the
ADM9690 are 4.3 V and 4.5 V.
Watchdog T imer
RESET
T he watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an infinite
loop. An output line on the processor may be used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, both
RESET
outputs are taken active
(low).
RESET(1)
remains low for 50 ms and
RESET(2)
remains low for an additional 10 ms . Each transition (either
positive-going or negative-going) of WDI after
RESET(1)
has
gone inactive restarts the watchdog timer. T he actual watchdog
timeout period is adjustable using SEL1 and SEL2. Four timeout
periods are selectable. Please refer to T able I.
T he watchdog timer is restarted at the end of
RESET(1)
(
RESET(1)
going high), whether the reset was caused by lack of
activity on WDI or by V
MON
falling below the reset threshold.
T able I.
Watchdog T imeout
Period t
WD
(ms)
0.75
1.5
12.5
25
SE L2
SE L1
0
0
1
1
0
1
0
1
V
MON
t
2
t
1
RESET(1)
RESET(2)
Figure 7. Power-On
RESET
Timing
WDI
t
2
t
1
RESET(1)
RESET(2)
t
WD
Figure 8. Watchdog
RESET
Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADM9690ARN-REEL | 制造商:Analog Devices 功能描述:Processor Supervisor 4.31V 4.31V 8-Pin SOIC N T/R |
| ADM9690ARNZ | 功能描述:IC SUPERVISOR PS/WATCHDOG 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應(yīng)商設(shè)備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| ADM9690ARNZ-REEL | 功能描述:IC SUPERVISOR PS/WATCHDOG 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:400 系列:- 類型:備用電池電路 監(jiān)視電壓數(shù)目:1 輸出:開路漏極，推挽式 復位:高有效/低有效 復位超時:最小為 35 ms 電壓 - 閥值:4.65V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:帶卷 (TR) 其它名稱:ADM691ARZ-REEL7TR |
| ADM-9F6-GR | 制造商:Pan Pacific 功能描述: |
| ADM-9F8-GR | 制造商:PAN PACIFIC 功能描述: |
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