CL = 50" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ADM3485ARZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 4/20闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC TXRX RS-485 HS 3.3V 8-SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 98
椤炲瀷锛� 鏀剁櫦(f膩)鍣�
椹�(q奴)鍕�(d貌ng)鍣�/鎺ユ敹鍣ㄦ暩(sh霉)锛� 1/1
瑕�(gu墨)绋嬶細 RS422锛孯S485
闆绘簮闆诲锛� 3 V ~ 3.6 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SO
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 790 (CN2011-ZH PDF)
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Data Sheet
Rev. E | Page 12 of 20
D
OUT
CL = 50pF2
GENERATOR1
50
S1
0V OR 3V
VCC
RL =110
05
52
4-
039
1PPR = 250kHz, 50% DUTY CYCLE,
tR 鈮� 6.0ns, ZO =50.
2CL INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 23. Driver Enable and Disable Times (tPZL, tPSL, tPLZ)
0
552
4-
0
40
GENERATOR1
50
CL =15pF2
R
1.5V
0
VOM =
VCC
2
OUT
VID
1PPR = 250kHz, 50% DUTY CYCLE,
tR 鈮� 6.0ns, ZO =50.
2CL INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 24. Receiver Propagation Delays
R
GENERATOR1
50
CL2
S3
S1
S2
VCC
+1.5V
鈥�1.5V
VID
1k
05
52
4-
04
1
1PPR = 250kHz, 50% DUTY CYCLE,
tR 鈮� 6.0ns, ZO =50.
2CL INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 25. Receiver Enable and Disable Times
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
ADM3485ARZ-REEL7 鍔熻兘鎻忚堪:IC TXRX RS485/422 HS 3.3V 8-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 椹�(q奴)鍕�(d貌ng)鍣�锛屾帴鏀跺櫒锛屾敹鐧�(f膩)鍣� 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:121 绯诲垪:- 椤炲瀷:鏀剁櫦(f膩)鍣� 椹�(q奴)鍕�(d貌ng)鍣�/鎺ユ敹鍣ㄦ暩(sh霉):1/1 瑕�(gu墨)绋�:RS422锛孯S485 闆绘簮闆诲:3 V ~ 3.6 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:10-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:10-DFN锛�3x3锛� 鍖呰:绠′欢
ADM3485E 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 Transceiver
ADM3485E_10 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:?卤15 kV ESD-Protected, 3.3 V,12 Mbps, EIA RS-485/RS-422 Transceiver
ADM3485EAN 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:3 VOLT RS-485 HIGH ESD I.C. - Bulk 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:TRANSCEIVER RS485/422 3.3V 3485
ADM3485EANZ 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:3 VOLT RS-485 HIGH ESD I.C. - Bulk 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:TRANSCEIVER RS485/422 3.3V 3485
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