參數(shù)資料
型號(hào)： ADM3078EYRZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/20頁(yè)
文件大?。?/td> 0K
描述： TXRX 3V 15KV 500KBPS ESD 8-SOIC
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： RS422，RS485
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
Rev. E | Page 9 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC 1
RO 2
RE 3
DE 4
VCC
14
NC
13
A
12
B
11
DI 5
Z
10
GND 6
Y
9
GND 7
NC
8
NC = NO CONNECT
ADM3070E/
ADM3073E/
ADM3076E
TOP VIEW
(Not to Scale)
062
85
-00
4
VCC 1
RO 2
DI 3
GND 4
A
8
B
7
Z
6
Y
5
ADM3071E/
ADM3074E/
ADM3077E
TOP VIEW
(Not to Scale)
06
28
5-
00
5
RO 1
RE 2
DE 3
DI 4
VCC
8
B
7
A
6
GND
5
ADM3072E/
ADM3075E/
ADM3078E
TOP VIEW
(Not to Scale)
06
28
5-
00
6
Figure 4. ADM3070E/ADM3073E/ADM3076E
Pin Configuration
Figure 5. ADM3071E/ADM3074E/ADM3077E
Pin Configuration
Figure 6. ADM3072E/ADM3075E/ADM3078E
Pin Configuration
Table 7. Pin Function Descriptions
ADM3070E/
ADM3073E/
ADM3076E
Pin No.
ADM3071E/
ADM3074E/
ADM3077E
Pin No.
ADM3072E/
ADM3075E/
ADM3078E
Pin No.
Mnemonic
Description
2
1
RO
Receiver Output. When enabled, if (A B) ≥ 50 mV, RO is high. If
(A B) ≤ 200 mV, RO is low.
3
N/A
2
RE
Receiver Output Enable. A low level enables the receiver output.
A high level places it in a high impedance state. If RE is high and DE
is low, the device enters a low power shutdown mode.
4
N/A
3
DE
Driver Output Enable. A high level enables the driver differential
A and B outputs. A low level places it in a high impedance state. If
RE is high and DE is low, the device enters a low power shutdown mode.
5
3
4
DI
Driver Input. With a half-duplex part when the driver is enabled, a
logic low on DI forces A low and B high; a logic high on DI forces
A high and B low. With a full-duplex part when the driver is enabled,
a logic low on DI forces Y low and Z high; a logic high on DI forces
Y high and Z low.
6, 7
4
5
GND
Ground.
9
5
N/A
Y
Noninverting Driver Output.
N/A
6
A
Noninverting Receiver Input A and Noninverting Driver Output A.
12
8
N/A
A
Noninverting Receiver Input A.
10
6
N/A
Z
Inverting Driver Output.
N/A
7
B
Inverting Receiver Input B and Inverting Driver Output B.
11
7
N/A
B
Inverting Receiver Input B.
14
1
8
VCC
Power Supply, 3.3 V ± 10%. Bypass VCC to GND with a 0.1 μF capacitor.
1, 8, 13
N/A
NC
No Connect. Not internally connected; can be connected to GND.
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