f
參數(shù)資料
型號: ADM2482EBRWZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 15/20頁
文件大?。?/td> 0K
描述: IC TXRX RS485 ISO W/ESD 16SOIC
標(biāo)準(zhǔn)包裝: 400
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: RS422,RS485
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
配用: 811-2154-5-ND - XFRMR CONV ADM2482 5.0V IN
811-2153-5-ND - XFRMR CONV ADM2482 3.3V IN
ADM2482E/ADM2487E
Rev. A | Page 4 of 20
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
TRANSFORMER DRIVER
Oscillator Frequency
fOSC
400
500
600
kHz
VDD1 = 5.0 V
230
330
430
kHz
VDD1 = 3.3 V
Switch-On Resistance
RON
0.5
1.5
Ω
Start-Up Voltage
VSTART
2.2
2.5
V
COMMON-MODE TRANSIENT IMMUNITY1
25
kV/μs
VCM = 1 kV, transient
magnitude = 800 V
1 CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common-mode is slewed. The common-mode voltage slew rates
apply to both rising and falling common-mode voltage edges.
TIMING SPECIFICATIONS
TA = 40°C to +85°C, unless otherwise noted.
Table 2. ADM2482E
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DRIVER
Propagation Delay
tDPLH, tDPHL
100
ns
RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26
Output Skew
tDSKEW
8
ns
RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26
Rise Time/Fall Time
tDR, tDF
15
ns
RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26
Enable Time
tZL, tZH
120
ns
RL = 110 Ω, CL = 50 pF, see Figure 22 and Figure 28
Disable Time
tLZ, tHZ
150
ns
RL = 110 Ω, CL = 50 pF, see Figure 22 and Figure 28
RECEIVER
Propagation Delay
tPLH, tPHL
110
ns
CL = 15 pF, see Figure 23 and Figure 27
Output Skew
tSKEW
8
ns
CL = 15 pF, see Figure 23 and Figure 27
Enable Time
tZL, tZH
13
ns
RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 29
Disable Time
tLZ, tHZ
13
ns
RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 29
Table 3. ADM2487E
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DRIVER
Propagation Delay
tDPLH, tDPHL
250
700
ns
RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26
Output Skew
tDSKEW
100
ns
RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26
Rise Time/Fall Time
tDR, tDF
200
1100
ns
RDIFF = 54 Ω, CL = 100 pF, see Figure 21 and Figure 26
Enable Time
tZL, tZH
2.5
μs
RL = 110 Ω, CL = 50 pF, see Figure 22 and Figure 28
Disable Time
tLZ, tHZ
200
ns
RL = 110 Ω, CL = 50 pF, see Figure 22 and Figure 28
RECEIVER
Propagation Delay
tPLH, tPHL
200
ns
CL = 15 pF, see Figure 23 and Figure 27
Output Skew
tSKEW
30
ns
CL = 15 pF, see Figure 23 and Figure 27
Enable Time
tZL, tZH
13
ns
RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 29
Disable Time
tLZ, tHZ
13
ns
RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 29
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