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參數(shù)資料
| 型號： | ADM1033ARQZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Thermal Monitor and Fan Speed (RPM) Controller |
| 中文描述： | 熱監(jiān)測和風(fēng)扇轉(zhuǎn)速（RPM）控制器 |
| 文件頁數(shù)： | 27/40頁 |
| 文件大小： | 1164K |
| 代理商： | ADM1033ARQZ |
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ADM1033
FAN SPEED MEASUREMENT REGISTERS
The16-bit measurements listed in Table 25 are stored in the
TACH value registers.
Table 25. TACH Value Registers
Register
Description
0x4A
TACH Period, LSB
0x4B
TACH Period, MSB
READING FAN SPEED
Reading back the fan speed involves a 2-register read for each
measurement. The low byte should be read first. This freezes the
high byte until both high and low byte registers have been read,
preventing erroneous fan speed measurement readings.
Rev. 0 | Page 27 of 40
Default
0xFF
0xFF
The fan tachometer reading registers report back the number of
12.20 μs period clocks (81.92 kHz oscillator) gated to the fan
speed counter for one full rotation of the fan (assuming the
correct number of poles is programmed). Because the
ADM1033 essentially measures the fan TACH period, the
higher the count value, the slower the fan’s actual speed. A 16-
bit fan TACH reading of 0xFFFF indicates that the fan has
stalled or is running very slowly (<75 rpm).
CALCULATING FAN SPEED
Fan speed in rpm is calculated as follows. This calculation
assumes the number of poles programmed in Configuration
Register 3 (Address 0x03) is correct for the fan used.
Fan Speed
(
rpm
) = (81920 × 60)/
Fan TACH Reading
where the Fan TACH Reading is the 16-bit Fan Tachometer
Reading.
Example:
TACH High Byte
(
Reg.
0×28) = 0×7
TACH Low Byte
(
Reg.
0×29) = 0×FF
What is the fan speed in rpm
Fan TACH Reading
= 0×17FF = 6143d
rpm
= (
f
× 60)/
Fan TACH Reading
rpm
= (81920 × 60)/6143
Fan Speed
= 800
rpm
ALARM SPEED
The fan ALARM speed (Bit 6) in Status Register 3 (Address 0x51)
is set whenever the fan runs at alarm speed. This occurs if the
device is programmed to run the fan at full speed whenever the
THERM temperature limits are exceeded. The device runs at
alarm speed, for example, if the Boost Disable bit (Bit 1) of the
Configuration 2 Register (Address 0x02) is not set to 1.
Fan Response Register
The ADM1033 fan speed controller operates by reading the
current fan speed, comparing it with the programmed fan
speed, and then updating the drive signal applied to the fan. The
fan response register determines the rate at which the
ADM1033 looks at and updates the drive signal. Different fans
have different inertias and respond to a changing drive signal
more or less quickly than others. The fan’s response register
allows the user to tailor the ADM1033 to a particular fan, to
prevent situations like overshoot.
The user selects the number of updates to the drive signal per
second. Table 26 lists the available options.
Table 26. Fan Response Codes
Code
Update Rate
000
1.25 updates/s
001
2.5 updates/s = default
010
5 updates/s
011
10 updates/s
100
20 updates/s
101
40 updates/s
110
80 updates/s
111
160 updates/s
Table 27. Fan Response Register (Address 0x3C)
Bit
<7:3>
<2:0>
Function
Unused
Fan Response
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