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參數(shù)資料
| 型號： | ADM1025ARQZ-R7 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MONITOR SYS/VOLT 5CH 16QSOP |
| 產(chǎn)品變化通告： | MFG CHG Notification ADI to ON Semi Product Obsolescence 11/Feb/2009 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 應(yīng)用： | PC，PDA |
| 接口： | I²C |
| 電源電壓： | 3 V ~ 5.5 V |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
ADM1025, ADM1025A
http://onsemi.com
8
reset output or interrupt output. Use of these functions may
restrict the addresses that can be set. See the sections on RST
and INT for further information.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high-to-low
transition on the serial data line SDA while the
serial clock line SCL remains high. This indicates
that an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the START condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus
an R/W bit, which determines the direction of the
data transfer, i.e., whether data will be written to
or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the Acknowledge Bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W bit is a 0, the master will
write to the slave device. If the R/W bit is a 1, the
master will read from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, since a low-to-high
transition when the clock is high may be
interpreted as a STOP signal. The number of data
bytes that can be transmitted over the serial bus in
a single READ or WRITE operation is limited
only by what the master and slave devices can
handle.
3. When all data bytes have been read or written,
STOP conditions are established. In WRITE mode,
the master will pull the data line high during the
10th clock pulse to assert a STOP condition. In
READ mode, the master device will override the
Acknowledge Bit by pulling the data line high
during the low period before the 9th clock pulse.
This is known as No Acknowledge. The master
will then take the data line low during the low
period before the 10th clock pulse, then high
during the 10th clock pulse to assert a STOP
condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
In the case of the ADM1025/ADM1025A, write
operations contain either one or two bytes, and read
operations contain one byte and perform the following
functions.
To write data to one of the device data registers or read
data from it, the Address Pointer Register must be set so that
the correct data register is addressed; data can then be
written into that register or read from it. The first byte of a
write operation always contains an address that is stored in
the Address Pointer Register. If data is to be written to the
device, the write operation contains a second data byte that
is written to the register selected by the Address Pointer
Register.
This is illustrated in Figure 10. The device address is sent
over the bus followed by R/W set to 0. This is followed by
two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
Address Pointer Register. The second data byte is the data to
be written to the internal data register.
Figure 10. Writing a Register Address to the Address Pointer Register,
then Writing Data to the Selected Register
R/W
0
SCL
SDA
10
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1025
START BY
MASTER
19
1
ACK. BY
ADM1025
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1025
STOP BY
MASTER
1
9
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
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