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參數(shù)資料
| 型號： | ADM1022 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low-Cost PC Temperature Monitor and Fan Control ASIC |
| 中文描述： | 低價電腦溫度監(jiān)控和風扇控制ASIC |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 190K |
| 代理商： | ADM1022 |
REV. 0
ADM1022
–15–
5 V OPERATION
The ADM1022 may be operated with V
CC
and/or V
MON
con-
nected to any supply voltage between 3.0 V and 5.5 V, but it
should be noted that the reset threshold voltages are fixed and
optimized for 3.3 V operation. If the V
CC
supply voltage is 5 V,
for example, the V
MON
input can still be used to monitor another
3.3 V supply without problems. However, the reset threshold for
the 5 V, V
CC
supply, may be below that at which 5 V logic will
operate reliably and may not give a reliable indication of brown-
out on the 5 V supply.
Alternatively, V
MON
may be configured to monitor a supply volt-
age higher than 3.3 V by adding an input attenuator.
The ratio of R1 to R2 is given by:
R
1/
R
2 = (
V
R
– 2.93)/2.93
Where
V
R
is the desired reset voltage and 2.93 V is the nominal
reset voltage of the V
MON
input.
R1
R2
V
MON
V
IN
Figure 20. Scaling V
MON
to a Higher Reset Voltage
The input resistance of the V
MON
input is approximately 100 k
,
with a tolerance of around
±
30%, so the parallel combination of
R1 and R2 should be much lower than 100 k
to minimize
errors due to variations in this input resistance.
INITIALIZATION (SOFT RESET)
Soft reset performs a similar, but not identical, function to
power-on reset. The Test Register and Analog Output register
are not initialized.
Soft reset is accomplished by setting Bit 4 of the Configuration
Register high. This bit automatically clears after being set.
NAND TREE TEST
A NAND tree is provided in the ADM1022 for Automated Test
Equipment (ATE) board level connectivity testing. The device
is placed into NAND tree test mode by powering up with pin
FAN_SPD/NTEST_IN (Pin 8) held high. This pin is sampled
and its state at power-up is latched. If it is connected high, the
NAND tree test mode is invoked. NAND tree test mode will
only be exited once the ADM1022 is powered down.
In NAND tree test mode, all digital inputs may be tested as illus-
trated in Table III. ADD/NTEST_OUT will become the NAND
tree output pin.
The structure of the NAND Tree is shown in Figure 21. To
perform a NAND Tree test, all pins are initially driven low. The
test vectors set all inputs low, then one-by-one toggles them
high (keeping them high). Exercising the test circuit with this
“walking one” pattern, starting with the input closest to the out-
put of the tree, cycling towards the farthest, causes the output of
the tree to toggle with each input change. Allow for a typical
propagation delay of 500 ns.
LATCH
D
Q
CLK
POWER-ON
RESET
ENABLE
GPI
SCL
SDA
MR
ADD/NTEST_OUT
FAN_SPD/
NTEST_IN
Figure 21. NAND Tree
Table III. Test Vectors
GPI
SCL
SDA
MR
ADD/NTEST_OUT
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
0
1
CONFIGURING THE INTERRUPT
On power-up, the Interrupt functionality of the device is disabled.
The Configuration Register (0x40) must be written to, in order
to enable the Interrupt output. The
INT
_Clear bit (Bit 2) should
be cleared to 0 and the
INT
_Enable bit (Bit 1) of the Register
should be set to 1.
If the
INT
_Enable bit is set, and the
INT
_Clear bit is not
cleared to 0, then any interrupts generated will be reflected in
the Interrupt Status Register, but will not toggle the Interrupt
pin externally.
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