參數(shù)資料
型號(hào)： ADM00421
廠商： Microchip Technology
文件頁(yè)數(shù)： 18/82頁(yè)
文件大?。?/td> 0K
描述： KIT EVALUATION MCP2210
產(chǎn)品培訓(xùn)模塊： MCP2210 Evaluation Kit
設(shè)計(jì)資源： ADM00421 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，USB 至 SPI
嵌入式： 否
已用 IC / 零件： MCP2210
主要屬性： 全速（12Mbps）
次要屬性： USB 供電
已供物品： 2 板，線纜
2011 Microchip Technology Inc.
DS22288A-page 25
MCP2210
FIGURE 3-6:
GET SPI POWER-UP TRANSFER SETTINGS LOGIC FLOW
14
Last Data Byte to CS (De-asserted) Delay (quanta of 100 s) – 16-bit value (low byte)
Example: If a 500 s delay between the last data byte sent and the CS being de-asserted is required,
the value will be 0x0005.
- This byte position will have a value of: 0x05
15
Last Data Byte to CS (De-asserted) Delay (quanta of 100 s) – 16-bit value (high byte)
Example: If a 500 s delay between the last data byte sent and the CS being de-asserted is required,
the value will be 0x0005.
- This byte position will have a value of: 0x00
16
Delay Between Subsequent Data Bytes (quanta of 100 s) – 16-bit value (low byte)
Example: If a 500 s delay between two consecutive data bytes is required, the value will be 0x0005.
- This byte position will have a value of: 0x05
17
Delay Between Subsequent Data Bytes (quanta of 100 s) – 16-bit value (high byte)
Example: If a 500 s delay between two consecutive data bytes is required, the value will be 0x0005.
- This byte position will have a value of: 0x00
18
Bytes to Transfer per SPI Transaction – 16-bit value (low byte)
Example: If an SPI transaction of 1250 bytes long is required, the corresponding hex value
will be 0x04E2.
- This byte position will have a value of: 0xE2
19
Bytes to Transfer per SPI Transaction – 16-bit value (high byte)
Example: If an SPI transaction of 1250 bytes long is required, the corresponding hex value
will be 0x04E2
- This byte position will have a value of: 0x04
20
SPI Mode
0x00 – SPI mode 0
0x01 – SPI mode 1
0x02 – SPI mode 2
0x03 – SPI mode 3
21 - 63
Don’t care
TABLE 3-18:
RESPONSE 1 STRUCTURE (CONTINUED)
Byte
Index
Meaning
Get NVRAM SPI
Transfer Settings
Response 1
NVRAM SPI
Transfer Settings
Retrieved
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