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參數(shù)資料
| 型號： | ADL5358XCPZ-WP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 混頻器 |
| 英文描述： | 500 MHz - 1700 MHz RF/MICROWAVE DOUBLE BALANCED MIXER |
| 封裝： | 6 X 6 MM, MO-220VJJD-1, LFCSP-36 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 360K |
| 代理商： | ADL5358XCPZ-WP |
Preliminary Technical Data
ADL5358
REV. PrE | Page 5 of 10
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADL5358
TOP VIEW
(Not to Scale)
24
25
26
23
22
21
1
2
3
9
20
27
19
VGS0
VGS1
VGS2
LOSW
PWDN
VPOS
COMM
LOI2
LOI1
4
5
6
7
8
MNIN
MNCT
COMM
DVIN
VPOS
COMM
VPOS
COMM
DVCT
1
0
1
2
1
3
1
4
1
5
1
6
1
7
1
8
V
P
O
S
D
V
G
M
C
O
M
D
V
O
P
D
V
O
N
D
V
L
E
V
P
O
S
D
V
L
G
N
C
3
4
3
5
3
6
3
2
3
1
3
0
2
9
2
8
M
N
O
N
C
O
M
N
G
M
V
P
O
S
M
N
O
P
M
N
L
E
V
P
O
S
M
N
L
G
N
C
06
66
1
-00
2
PIN 1
INDICATOR
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Function
1
MNIN
RF Input for Main Channel. Internally matched to 50
Ω. Must be ac-coupled.
2
MNCT
Center Tap for Main Channel Input Balun. Should be bypassed to ground using low inductance capacitor.
3, 5, 7,
12, 20,
34
COMM
Device Common (DC Ground).
4,, 6, 10,
16, 21,
30, 36
VPOS
Positive Supply Voltage.
8
DVCT
Center Tap for Diversity Channel Input Balun. Should be bypassed to ground using low inductance capacitor.
9
DVIN
RF Input for Diversity Channel. Internally matched to 50
Ω. Must be ac-coupled.
11
DVGM
Diverstiy Amplifier Bias Setting. Connect 1.2k
Ω resistor to ground for typical operation.
13, 14
DVOP, DVON
Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to VCC using
pull-up choke inductors.
15
DVLE
Diversity Channel External Inductor. Connect 10nH inductor to ground for typical operation.
17
DVLG
Diverstiy Channel LO Buffer Bias Setting. Connect 390
Ω resistor to ground for typical operation.
18, 28
NC
No Connect.
19,
L0I1
Local Oscillator Input 1. Internally matched to 50
Ω. Must be ac-coupled.
22
PWDN
Connect to Ground for Normal Operation. Connect pin to 3.3V for disable mode.
23
LOSW
Local Oscillator Input Selection Switch. Set LOSW high to select LOI1, and set low to select LOI2.
24, 25,
26
VGS0, VGS1,
VGS2
Gate to Source Control Voltages. For typical operation set VGS2 high and VGS0 and VGS1 to low logic level.
27
LOI2
Local Oscillator Input 2. Internally matched to 50
Ω. Must be ac-coupled.
29
MNLG
Main Channel LO Buffer Bias Setting. Connect 390
Ω resistor to ground for typical operation.
31
MNLE
Main Channel External Inductor. Connect 10nH inductor to ground for typical operation.
32, 33
MNOP, MNON
Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to VCC using pull-
up choke inductors.
35
MNGM
Main Amplifier Bias Setting. Connect 1.2k
Ω resistor to ground for typical operation.
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