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參數(shù)資料
| 型號： | ADJD-S312-CR999 |
| 廠商： | Avago Technologies Ltd. |
| 英文描述： | Miniature Surface-Mount RGB Digital Color Sensor |
| 中文描述： | 微型表面貼裝RGB數(shù)字色彩傳感器 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ADJD-S312-CR999 |
1
AVDD
A1
DGND
C2
DVDD
D1
AGND
XRST
SDASLV
SCLSLV
Voltage
Regulator
Voltage
Regulator
HOST
SYSTEM
XRST
SDA
SCL
Star-connected ground
SLEEP
1
HOST
SYSTEM
1
1
1
DVDD
A4
D4
C4
C3
A2, A3,
D2
Pin
A1
Name
AVDD
Type
Power
Description
Analog power pin.
A2
AGND
Ground
Tie to analog ground.
A3
AGND
Ground
Tie to analog ground.
A4
SLEEP
Input
When SLEEP=1, the device goes into sleep mode. In sleep mode, all analog circuits are
powered down and the clock signal is gated away from the core logic resulting in very
low current consumption.
B1
NC
No connect
No connect. Leave floating.
B2
NC
No connect
No connect. Leave floating.
B3
NC
No connect
No connect. Leave floating.
B4
NC
No connect
No connect. Leave floating.
C1
NC
No connect
No connect. Leave floating
C2
DGND
Ground
Tie to digital ground.
C3
SCLSLV
Input
SDASLV and SCLSLV are the serial interface communications pins. SDASLV is the bidi-
rectional data pin and SCLSLV is the interface clock. A pull-up resistor should be tied to
SDASLV because it goes tri-state to output logic 1.
C4
SDASLV
Input/
Output(tri-state
high)
Power
D1
DVDD
Digital power pin.
D2
AGND
Ground
Tie to analog ground.
D3
NC
No connect
No connect. Leave floating.
D4
XRST
Input
Global, asynchronous, active-low system reset. When asserted low, XRST resets all regis-
ters. Minimum reset pulse low is 1 us and must be provided by external circuitry.
Application Diagrams
Powering the Device
Ground Connection
AGND and DGND must both be set to 0V and preferably
star-connected to a central power source as shown in
the application diagram. A potential difference between
AGND and DGND may cause the ESD diodes to turn on
inadvertently.
Pin Information
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