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參數(shù)資料
| 型號： | ADG804YRM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 0.5 ohm CMOS 1.65 V TO 3.6 V 4-Channel Multiplexer |
| 中文描述： | 4-CHANNEL, SGL ENDED MULTIPLEXER, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 157K |
| 代理商： | ADG804YRM-REEL7 |
ADG804
PIN CONFIGURATION
Rev. 0 | Page 7 of 16
NC = NO CONNECT
ADG804
TOP VIEW
(Not to Scale)
A0
1
S1
2
GND
3
S3
4
EN
5
A1
S2
D
S4
V
DD
10
9
8
7
6
0
Figure 2. 10-Lead MSOP (RM-10)
Table 6. Terminology
V
DD
I
DD
GND
S
D
EN
A0, A1
V
D
, V
S
R
ON
R
FLAT (ON)
Most positive power supply potential.
Positive supply current.
Ground (0 V) reference.
Source terminal. May be an input or an output.
Drain terminal. May be an input or an output.
Active high logic control input.
Logic control inputs. Used to select which source terminal, S1 to S4, is connected to the drain, D.
Analog voltage on terminals D, S.
Ohmic resistance between D and S.
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the
specified analog signal range.
On resistance match between any two channels.
Source leakage current with the switch off.
Drain leakage current with the switch off.
Channel leakage current with the switch on.
Maximum input voltage for Logic 0.
Minimum input voltage for Logic 1.
Input current of the digital input.
Off switch source capacitance. Measured with reference to ground.
Off switch drain capacitance. Measured with reference to ground.
On switch capacitance. Measured with reference to ground.
Digital input capacitance.
Delay time between the 50% and the 90% points of the digital input and switch on condition.
Delay time between the 50% and the 90% points of the digital input and switch off condition.
Delay time between the 50% and the 90% points of the digital input and switch on condition when switching from one
address state to the other.
On or off time measured between the 80% points of both switches when switching from one to another.
A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching.
A measure of unwanted signal coupling through an off switch.
A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance.
The frequency at which the output is attenuated by 3 dB.
The frequency response of the on switch.
The loss due to the on resistance of the switch.
The ratio of the harmonic amplitudes plus noise of a signal to the fundamental.
R
ON
I
S
(OFF)
I
D
(OFF)
I
D
, I
S
(ON)
V
INL
V
INH
I
INL
(I
INH
)
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
C
IN
t
ON
(EN)
t
OFF
(EN)
t
TRANSITION
t
BBM
Charge Injection
Off Isolation
Crosstalk
3 dB Bandwidth
On Response
Insertion Loss
THD + N
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