Parameter1 Conditions Min Max Unit Description t" />
參數(shù)資料
型號: ADG795ABCPZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 23/24頁
文件大?。?/td> 0K
描述: IC MUX/DEMUX 2X1 24LFCSP
產(chǎn)品變化通告: ADG79xx Discontinuance Notice 17/Aug/2010
標(biāo)準(zhǔn)包裝: 1
功能: 多路復(fù)用器/多路分解器
電路: 5 x 2:1
導(dǎo)通狀態(tài)電阻: 4 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3V,5V
電流 - 電源: 1nA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 801 (CN2011-ZH PDF)
其它名稱: ADG795ABCPZ-REELDKR
ADG795A/ADG795G
Rev. 0 | Page 8 of 24
Parameter1
Conditions
Min
Max
Unit
Description
t11
Standard mode
1000
ns
tRCL, rise time of SCL signal
Fast mode
20 + 0.1 CB
300
ns
High speed mode
CB = 100 pF max
10
40
ns
CB = 400 pF max
20
80
ns
t11A
Standard mode
1000
ns
tRCL1, rise time of SCL signal after a repeated start condition
and after an acknowledge bit
Fast mode
20 + 0.1 CB
300
ns
High speed mode
CB = 100 pF max
10
80
ns
CB = 400 pF max
20
160
ns
t12
Standard mode
300
ns
tFCL, fall time of SCL signal
Fast mode
20 + 0.1 CB
300
ns
High speed mode
CB = 100 pF max
10
40
ns
CB = 400 pF max
20
80
ns
tSP
Fast mode
0
50
ns
Pulse width of suppressed spike
High speed mode
0
10
ns
1Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD.
2A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
SCL
SDA
PS
S
P
t8
t6
t5
t3
t10
t9
t4
t6
t1
t7
t2
t11
t12
0
60
34
-00
2
Figure 2. Timing Diagram for 2-Wire Serial Interface
OBSOLETE
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