參數(shù)資料
型號: ADG621BRM
廠商: ANALOG DEVICES INC
元件分類: 運動控制電子
英文描述: CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES
中文描述: DUAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO10
封裝: MO-187BA, MSOP-10
文件頁數(shù): 5/12頁
文件大小: 141K
代理商: ADG621BRM
REV. 0
ADG621/ADG622/ADG623
–5–
TERMINOLOGY
V
DD
V
SS
Most Positive Power Supply Potential.
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied
to ground at the device.
Ground (0 V) Reference
Positive Supply Current
Negative Supply Current
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Ohmic resistance between D and S.
On resistance match between any two Channels i.e., R
ON
max
R
ON
min.
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured
over the specified analog signal range.
Source Leakage Current with the switch
OFF.
Drain Leakage Current with the switch
OFF.
Channel Leakage Current with the switch
ON.
Analog Voltage on Terminals D, S.
Maximum Input Voltage for Logic
0.
Minimum Input Voltage for Logic
1.
Input Current of the Digital Input
OFF
Switch Source Capacitance
OFF
Switch Drain Capacitance
ON
Switch Capacitance
Delay between applying the digital control input and the output switching on.
Delay between applying the digital control input and the output switching off.
OFF
time or
ON
time measured between the 90% points of both switches, when switching from one
address state to another.
A measure of the Glitch Impulse transfered from the Digital input to the Analog output during switching.
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
capacitance.
A measure of unwanted signal coupling through an
OFF
switch.
The frequency response of the
ON
switch.
The loss due to the ON resistance of the Switch.
GND
I
DD
I
SS
S
D
IN
R
ON
R
ON
R
FLAT(ON)
I
S
(OFF)
I
D
(OFF)
I
D
, I
S
(ON)
V
D
(V
S
)
V
INL
V
INH
I
INL
(I
INH
)
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
t
ON
t
OFF
t
BBM
Charge Injection
Crosstalk
Off Isolation
Bandwidth
Insertion Loss
PIN CONFIGURATION
10-Lead SOIC
(RM-10)
TOP VIEW
(Not to Scale)
10
9
8
7
6
1
2
3
4
5
NC = NO CONNECT
D1
S1
GND
S2
IN1
V
DD
ADG621/
ADG622/
ADG623
V
SS
NC
D2
IN2
相關PDF資料
PDF描述
ADG622 CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES
ADG622BRM CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES
ADG623 CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES
ADG623BRM CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES
ADG621 CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES
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