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參數(shù)資料
| 型號： | ADG528ATQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC MULTIPLEXER 8X1 18CDIP |
| 產(chǎn)品培訓(xùn)模塊： | Switch Fundamentals |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 功能： | 多路復(fù)用器 |
| 電路： | 1 x 8:1 |
| 導(dǎo)通狀態(tài)電阻： | 700 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 10.8 V ~ 16.5 V，±10.8 V ~ 16.5 V |
| 電流 - 電源： | 600µA |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 18-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 18-CDIP |
| 包裝： | 管件 |
REV. B
–6–
ADG528A/ADG529A
TRUTH TABLES
A2 A1 A0 EN
WR RS ON SWITCH PAIR
XXXX
1Retains Previous Switch Condition
XXXX
X
0
NONE (Address and Enable
Latches Cleared)
XXX0
0
1
NONE
0001
0
1
0011
0
1
2
0101
0
1
3
0111
0
1
4
1001
0
1
5
1011
0
1
6
1101
0
1
7
1111
0
1
8
X = Don’t Care
ADG528A
A1 A0 EN
WR RS ON SWITCH PAIR
XXX
1Retains Previous Switch Condition
XXX
X0
NONE (Address and Enable Latches
Cleared)
XX0
01
NONE
001
0
1
011
0
1
2
101
0
1
3
111
0
1
4
X = Don’t Care
ADG529A
TIMING DIAGRAMS
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while
WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of
WR.
Figure 2 shows the Reset Pulse Width, tRS, and Reset Turn-off
Time, tOFF (RS).
Note: All digital input signals rise and fall times measured from
10% to 90% of 3 V. tR = tF = 20 ns.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADG528ATQ/883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Channel Analog Multiplexer |
| ADG528F | 制造商:AD 制造商全稱:Analog Devices 功能描述:4/8 Channel Fault-Protected Analog Multiplexers |
| ADG528FBN | 制造商:Analog Devices 功能描述:Analog Multiplexer Single 8:1 18-Pin PDIP N 制造商:Analog Devices 功能描述:IC MUX 8 CHANNEL 制造商:Analog Devices 功能描述:4/8 Channel Fault-Protected Analog Multiplexers |
| ADG528FBNZ | 制造商:Analog Devices 功能描述:Analog Multiplexer Single 8:1 18-Pin PDIP N 制造商:Analog Devices 功能描述:Analog MUX Single 8:1 18-Pin PDIP |
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