參數(shù)資料
型號: ADG444BRZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 4/16頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 16SOIC
產(chǎn)品培訓(xùn)模塊: Switch Fundamentals
標(biāo)準(zhǔn)包裝: 2,500
系列: LC²MOS
功能: 開關(guān)
電路: 4 x SPST - NC
導(dǎo)通狀態(tài)電阻: 110 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 12V,±15V
電流 - 電源: 1nA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
ADG441/ADG442/ADG444
Rev. A | Page 12 of 16
TRENCH ISOLATION
In the ADG441A, ADG442A, and ADG444A, an insulating
oxide layer (trench) is placed between the NMOS and the
PMOS transistors of each CMOS switch. Parasitic junctions,
which occur between the transistors in junction isolated
switches, are eliminated, and the result is a completely latch-up
proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward-biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
05233-
004
BURIED OXIDE LAYER
SUBSTRATE (BACK GATE)
TRENCH
P-WELL
N-WELL
LOCO
NMOS
PMOS
Figure 21. Trench Isolation
相關(guān)PDF資料
PDF描述
RPE5C2A680J2P1Z03B CAP CER 68PF 100V 5% RADIAL
ADG721BRM-REEL7 IC SWITCH DUAL SPST 8MSOP
RPE5C2A680J2K1Z03B CAP CER 68PF 100V 5% RADIAL
GRM31C5C1H104FA01L CAP CER 0.1UF 50V 1% NP0 1206
ADG701LBRJZ-500RL7 IC SWITCH SPST CMOS SOT23-5
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADG444BRZ-REEL1 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Quad SPST Switches ADG441/ADG442/ADG444
ADG445BQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
ADG445TQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
ADG451 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS 5 ohm RON SPST Switches
ADG451_06 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS 5 ?? RON SPST Switches