參數(shù)資料
型號(hào): ADG441BNZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 4/16頁(yè)
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 16DIP
產(chǎn)品培訓(xùn)模塊: iCMOS™ Switches and Multiplexers for Data Acquisition
Switch Fundamentals
標(biāo)準(zhǔn)包裝: 25
系列: LC²MOS
功能: 開(kāi)關(guān)
電路: 4 x SPST - NC
導(dǎo)通狀態(tài)電阻: 110 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 12V,±15V
電流 - 電源: 1nA
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-PDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 800 (CN2011-ZH PDF)
ADG441/ADG442/ADG444
Rev. A | Page 12 of 16
TRENCH ISOLATION
In the ADG441A, ADG442A, and ADG444A, an insulating
oxide layer (trench) is placed between the NMOS and the
PMOS transistors of each CMOS switch. Parasitic junctions,
which occur between the transistors in junction isolated
switches, are eliminated, and the result is a completely latch-up
proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward-biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
05233-
004
BURIED OXIDE LAYER
SUBSTRATE (BACK GATE)
TRENCH
P-WELL
N-WELL
LOCO
NMOS
PMOS
Figure 21. Trench Isolation
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