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參數(shù)資料
| 型號： | ADG3301BKSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 0K |
| 描述： | TRANSLATOR SGL LL BIDIR SC70-6 |
| 標準包裝： | 1 |
| 邏輯功能： | 變換器，雙向 |
| 位數(shù)： | 1 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 數(shù)據速率： | 50Mbps |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 6ns |
| 電源電壓： | 1.15 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 供應商設備封裝： | SC-70 |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 802 (CN2011-ZH PDF) |
| 其它名稱： | ADG3301BKSZ-REEL7DKR |
ADG3301
Rev. 0 | Page 16 of 20
THEORY OF OPERATION
The ADG3301 level translator allows the level shifting
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, VCCA and
VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each
side of the device. When driving the A pin, the device translates
the VCCA-compatible logic levels to VCCY-compatible logic levels
available at the Y pin. Similarly, because the device is capable of
bidirectional translation, when driving the Y pin the VCCY-com-
patible logic levels are translated to VCCA-compatible logic levels
available at the A pin. When EN = 0, the A pin and the Y pin
are three-stated. When EN is driven high, the ADG3301 goes
into normal operation mode and performs level translation.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3301 consists of a single bidirectional channel that can
translate logic levels in either the A→Y or the Y→A direction.
It uses a one-shot accelerator architecture that ensures excellent
switching characteristics. Figure 37 shows a simplified block
diagram of the ADG3301 level translator.
ONE-SHOT GENERATOR
6k
6k
Y
VCCA
VCCY
T2
T1
T3
T4
A
05517-037
P
N
U1
U2
U4
U3
Figure 37. Simplified Block Diagram of an ADG3301 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y→A direction is performed using the
inverters U3 and U4. The one-shot generator detects a rising
or falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS transis-
tors (T1 and T2) for a rising edge, or the NMOS transistors
(T3 and T4) for a falling edge. This charges/discharges the
capacitive load faster, which results in fast rise and fall times.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3301, the circuit that
drives the input of an ADG3301 channel must have an output
impedance of less than or equal to 150 and a minimum peak
current driving capability of 36 mA.
OUTPUT LOAD REQUIREMENTS
The ADG3301 level translator is designed to drive CMOS-
compatible loads. If current driving capability is required, it is
recommended to use buffers between the ADG3301 outputs
and the load.
ENABLE OPERATION
The ADG3301 provides three-state operation at the A I/O pin
and Y I/O pin by using the enable (EN) pin as shown in Table 4.
Table 4. Truth Table
EN
Y I/O Pin
A I/O Pin
0
Hi-Z1
1
Normal operation2
1 High impedance state.
2 In normal operation, the ADG3301 performs level translation.
While EN = 0, the ADG3301 enters into tri-state mode. In this
mode, the current consumption from both the VCCA and VCCY
supplies is reduced, allowing the user to save power, which is
critical especially on battery-operated systems. The EN input pin
can be driven with either VCCA- or VCCY-compatible logic levels.
POWER SUPPLIES
For proper operation of the ADG3301, the voltage applied to
the VCCA must be always less than or equal to the voltage applied
to VCCY. To meet this condition, the recommended power-up
sequence is VCCY first and then VCCA. The ADG3301 operates
properly only after both supply voltages reach their nominal
values. It is not recommended to use the part in a system where,
during power-up, VCCA may be greater than VCCY due to a
significant increase in the current taken from the VCCA supply
For optimum performance, the VCCA and VCCY pins should be
decoupled to GND, and placed as close as possible to the device.
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