參數(shù)資料
型號(hào)： ADG1438BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 0K
描述： IC MULTIPLEXER 8:1 20TSSOP
標(biāo)準(zhǔn)包裝： 75
系列： iCMOS®
功能： 多路復(fù)用器
電路： 1 x 8:1
導(dǎo)通狀態(tài)電阻： 21.5 歐姆
電壓電源： 單/雙電源
電壓 - 電源，單路/雙路(±)： 5 V ~ 16.5 V，±2.25 V ~ 8.25 V
電流 - 電源： 1nA
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 802 (CN2011-ZH PDF)
ADG1438/ADG1439
Rev. A | Page 19 of 20
THEORY OF OPERATION
The ADG1438 and ADG1439 are serially controlled, 8-channel
and dual 4-channel matrix switches, respectively. While
providing the normal multiplexing and demultiplexing
functions, these devices also provide the user with more
flexibility as to where a signal can be routed. Each of the eight
bits of the 8-bit write corresponds to one switch of the device.
Logic 1 in a particular bit position turns the switch on, whereas
Logic 0 turns the switch off. Because each switch is
independently controlled by an individual bit, this provides the
option of having any, all, or none of the switches on. This
feature may be particularly useful in the demultiplexing
application where the user may wish to direct one signal from
the drain to a number of outputs (sources). Care must be taken,
however, in the multiplexing situation where a number of
inputs may be shorted together (separated only by the small on
resistance of the switch).
SERIAL INTERFACE
The ADG1438/ADG1439 has a 3-wire serial interface (SYNC,
SCLK, and DIN pins) that is compatible with SPI, QSPI, and
MICROWIRE interface standards, as well as most DSPs (see
for a timing diagram of a typical write sequence).
The write sequence begins by bringing the SYNC line low. This
enables the input shift register. Data from the DIN line is clocked
into the 8-bit input shift register on the falling edge of SCLK.
The serial clock frequency can be as high as 50 MHz, making
the ADG1438/ADG1439 compatible with high speed DSPs.
Data can be written to the shift register in more or fewer than
eight bits. In each case, the shift register retains the last eight
bits that are written. When all eight bits are written into the
shift register, the SYNC line is brought high again. The switches
are updated with the new configuration, and the input shift
register is disabled. With SYNC held high, the input shift
register is disabled so that further data or noise on the DIN line
has no effect on the shift register.
Data appears on the SDO pin on the rising edge of SCLK,
suitable for daisy-chaining or readback, delayed by eight bits.
INPUT SHIFT REGISTER
The input shift register is eight bits wide, as shown in Table 12 and
Table 13. Each bit controls one switch. These data bits are
transferred to the switch register on the rising edge of SYNC.
Table 12. ADG1438 Input Shift Register Bit Map1
MSB
LSB
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
S8
S7
S6
S5
S4
S3
S2
S1
1 Logic 0 = switch off, and Logic 1 = switch on.
Table 13. ADG1439 Input Shift Register Bit Map1
MSB
LSB
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
S4B
S3B
S2B
S1B
S4A
S3A
S2A
S1A
1 Logic 0 = switch off, and Logic 1 = switch on.
POWER-ON RESET
The ADG1438/ADG1439 contain a power-on reset circuit. On
power-up of the device, all switches are off, and the internal
shift register is filled with zeros and remains so until a valid
write takes place.
The part also has a RESET pin. When the RESET pin is low, all
switches are off, and the appropriate registers are cleared to 0.
DAISY-CHAINING
For systems that contain several switches, the SDO pin can be
used to daisy-chain several devices together. The SDO pin can
also be used for diagnostic purposes and to provide serial
readback where the user wants to read back the switch contents.
The SDO pin is an open-drain output that should be pulled to
the VL supply with an external resistor.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than eight clock pulses are applied,
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next switch in the chain, a multiswitch interface is
constructed. Each switch in the system requires eight clock
pulses; therefore, the total number of clock cycles must equal
8N, where N is the total number of devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data from being clocked
into the input shift register.
The serial clock can be a continuous or a gated clock. A con-
tinuous SCLK source can be used only if SYNC can be held low
for the correct number of clock cycles. In gated clock mode, a
burst clock containing the exact number of clock cycles must be
used, and SYNC must be taken high after the final clock to latch
the data. Gated clock mode reduces power consumption by
reducing the active clock time.
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