V
參數(shù)資料
型號(hào): ADG1408YRUZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 2/20頁(yè)
文件大?。?/td> 0K
描述: IC MULTIPLEXER 8X1 16TSSOP
產(chǎn)品培訓(xùn)模塊: Power Line Monitoring
Switch Fundamentals
標(biāo)準(zhǔn)包裝: 2,500
系列: iCMOS®
功能: 多路復(fù)用器
電路: 1 x 8:1
導(dǎo)通狀態(tài)電阻: 8 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 5 V ~ 16.5 V,±2.25 V ~ 8.25 V
電流 - 電源: 220µA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
ADG1408/ADG1409
Rev. B | Page 10 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
VSS
S1
S4
S3
S2
A0
A2
GND
VDD
S7
DS
S6
S5
A1
ADG1408
TOP VIEW
(Not to Scale)
8
0
48
61
-00
2
Figure 2. ADG1408 Pin Configuration (TSSOP)
PIN 1
INDICATOR
1
VSS
NOTES
1. THE EXPOSED PAD IS
CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, VSS.
2
S1
3
S2
4
S3
11 VDD
12 GND
10 S5
9S6
5
S
4
6
D
7
S
8
S
7
15
A
0
16
E
N
14
A
1
13
A
2
TOP VIEW
(Not to Scale)
ADG1408
04
86
1-
0
03
Figure 3. ADG1408 Pin Configuration (LFCSP)
Table 8. ADG1408 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
15
A0
Logic Control Input.
2
16
EN
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3
1
VSS
Most Negative Power Supply Potential. In single supply applications, it can be connected
to ground.
4
2
S1
Source Terminal 1. Can be an input or an output.
5
3
S2
Source Terminal 2. Can be an input or an output.
6
4
S3
Source Terminal 3. Can be an input or an output.
7
5
S4
Source Terminal 4. Can be an input or an output.
8
6
D
Drain Terminal. Can be an input or an output.
9
7
S8
Source Terminal 8. Can be an input or an output.
10
8
S7
Source Terminal 7. Can be an input or an output.
11
9
S6
Source Terminal 6. Can be an input or an output.
12
10
S5
Source Terminal 5. Can be an input or an output.
13
11
VDD
Most Positive Power Supply Potential.
14
12
GND
Ground (0 V) Reference.
15
13
A2
Logic Control Input.
16
14
A1
Logic Control Input.
EP
Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG1408 Truth Table
A2
A1
A0
EN
On Switch
X
0
None
0
1
0
1
2
0
1
0
1
3
0
1
4
1
0
1
5
1
0
1
6
1
0
1
7
1
8
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