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參數(shù)資料
| 型號： | ADF4360-1BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24-LFCSP |
| 標準包裝： | 1 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 2.45GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
| 配用： | EVAL-ADF4360-1EBZ1-ND - BOARD EVALUATION FOR ADF4360-1 |
Data Sheet
ADF4360-1
Rev. C | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04414-
003
ADF4360-1
TOP VIEW
(Not to Scale)
CPGND
1
AVDD 2
AGND
3
RFOUTA 4
RFOUTB 5
VVCO 6
DATA
18
CLK
17
REFIN
16
DGND
15
CN
14
RSET
13
V
T
UNE
7
AG
ND
8
AG
ND
9
AG
ND
10
AG
ND
11
C
12
CP
24
CE
23
AG
ND
22
DV
DD
21
M
UX
O
UT
20
LE
19
PIN 1
IDENTIFIER
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2
AV
DD
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD must have the same value as DVDD.
3, 8 to 11, 22
AGND
Analog Ground. This is the ground return path of the prescaler and VCO.
4
RF
OUTA
VCO Output. The output level is programmable from 6 dBm to 13 dBm. See the Output Matching section
for a description of the various output stages.
5
RF
OUTB
VCO Complementary Output. The output level is programmable from 6 dBm to 13 dBm. See the Output
Matching section for a description of the various output stages.
6
V
VCO
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. V
VCO must have the same value as AVDD.
7
V
TUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
output voltage.
12
C
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13
R
SET
Connecting a resistor between this pin and CP
GND sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the R
SET pin is 0.6 V. The relationship between ICP and RSET is
SET
CPmax
R
I
75
.
11
=
where R
SET = 4.7 k, ICPMAX = 2.5 mA.
14
C
N
Internal Compensation Node. This pin must be decoupled to V
VCO with a 10 F capacitor.
15
DGND
Digital Ground.
16
REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD/2 and a dc equivalent input resistance of
100 k. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
17
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
21
DV
DD
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD must have the same value as AVDD.
23
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. Taking the pin high powers up the device depending on the status of the power-down bits.
24
CP
Charge Pump Output. When enabled, this provides ± I
CP to the external loop filter, which in turn drives the
internal VCO.
EP
Exposed Pad. The exposed pad must be connected to AGND.
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| ADF4360-1BCPZ | 制造商:Analog Devices 功能描述:INTEGRATED SYNTHESIZER |
| ADF4360-1BCPZ | 制造商:Analog Devices 功能描述:IC FREQ SYNTHESIZER 2450MHZ 24-LFCSP |
| ADF4360-1BCPZRL | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-1BCPZRL7 | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-1SP1BCPZ | 制造商:Analog Devices 功能描述: |
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