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參數(shù)資料
| 型號： | ADF4350BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/32頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTH PLL VCO FN/IN 32LFCSP |
| 產品變化通告： | ADF4350, ADF4905/6 N-counter Change 05/Mar/2012 |
| 設計資源： | Broadband Low EVM Direct Conversion Transmitter (CN0134) Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144) Using low noise linear drop-out regulators to power wideband PLL & VCO IC's (CN0147) |
| 標準包裝： | 1 |
| 類型： | 扇出配送，分數(shù)-N，整數(shù)-N，時鐘/頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
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ADF4350
Rev. A | Page 21 of 32
INITIALIZATION SEQUENCE
The following sequence of registers is the correct sequence for
initial power-up of the ADF4350 after the correct application of
voltages to the supply pins:
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
RF SYNTHESIZER—A WORKED EXAMPLE
The following is an example how to program the ADF4350
synthesizer:
RFOUT = [INT + (FRAC/MOD)] × [fPFD]/RF divider
(3)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
RF divider is the output divider that divides down the VCO
frequency.
fPFD = REFIN × [(1 + D)/(R × (1+T))]
(4)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
T is the reference divide-by-2 bit (0 or 1).
R is the RF reference division factor.
For example, in a UMTS system, where 2112.6 MHz RF
frequency output (RFOUT) is required, a 10 MHz reference
frequency input (REFIN) is available, and a 200 kHz channel
resolution (fRESOUT) is required on the RF output. Note that
the ADF4350 operates in the frequency range of 2.2 GHz to
4.4 GHz. Therefore, the RF divider of 2 should be used (VCO
frequency = 4225.2 MHz, RFOUT = VCO frequency/RF divider =
4225.2 MHz/2 = 2112.6 MHz).
It is also important where the loop is closed. In this example,
the loop is closed (see Figure 30).
fPFD
PFD
VCO
N
DIVIDER
÷2
0
73
25-
0
27
RFOUT
Figure 30. Loop Closed Before Output Divider
Channel resolution (fRESOUT) or 200 kHz is required at the output
of the RF divider. Therefore, channel resolution at the output of
the VCO (fRES) is to be twice the fRESOUT, that is 400 kHz.
MOD = REFIN/fRES
MOD = 10 MHz/400 kHz = 25
From Equation 4,
fPFD = [10 MHz × (1 + 0)/1] = 10 MHz
(5)
2112.6 MHz = 10 MHz × (INT + FRAC/25)/2
(6)
where:
INT = 422
FRAC = 13
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (fRES) required at
the RF output. For example, a GSM system with 13 MHz REFIN
sets the modulus to 65. This means the RF output resolution (fRES)
is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,
the fractional spur interval depends on the modulus values chosen
(see Table 6).
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important to
note that the PFD cannot operate above 32 MHz due to a limi-
tation in the speed of the Σ-Δ circuit of the N-divider.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the cycle slip reduction (CSR)
function. See the Cycle Slip Reduction for Faster Lock Times
section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4350 allows the
user to program the modulus over a 12–bit range. This means
the user can set up the part in many different configurations for
the application, when combined with the reference doubler and
the 10-bit R counter.
For example, consider an application that requires 1.75 GHz RF
and 200 kHz channel step resolution. The system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD programming the modulus to divide by 130. This
also results in 200 kHz resolution and offers superior phase
noise performance over the previous setup.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4350BCPZ-RL | 功能描述:IC SYNTH PLL VCO FN/IN 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4350BCPZ-RL7 | 功能描述:IC SYNTH PLL VCO FN/IN 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4350BCPZ-U6 | 制造商:Analog Devices 功能描述: |
| ADF4350EB1Z | 制造商:Analog Devices 功能描述:AD EVAL BOARD - Bulk |
| ADF4351 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Wideband Synthesizer |
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