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參數資料
| 型號： | ADF4212BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20-TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器（RF/IF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 2.7GHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
–17–
RF PROGRAM MODES
Table III and Table V show how to set up the Program Modes
in the ADF421x family.
RF Charge Pump Currents
RFCP2, RFCP1, RFCP0 program current setting for the RF
charge pump. See Table V.
PROGRAMMABLE RF N COUNTER
If control bits C2, C1 are 1, 1, the data in the input register is
used to program the RF N (A + B) counter. The N counter
consists of a 6-bit swallow counter (A Counter) and 12-bit
programmable counter (B Counter). Table IV shows the input
register data format for programming the RF N counter and the
possible divide ratios.
RF Prescaler Value
P14 and P15 in the RF A, B Counter Latch sets the RF pres-
caler value. See Table VI.
RF Power-Down
Table III and Table V show the power-down bits in the
ADF421x family.
RF Fastlock
The RF CP Gain bit (P17) of the RF N register in the ADF421x
family is the Fastlock Enable Bit. Only when this is “1” is IF
Fastlock enabled. When Fastlock is enabled, the RF CP current
is set to its maximum value. Also an extra loop lter damping
resistor to ground is switched in using the FL O pin, thus com-
pensating for the change in loop characteristics while in Fastlock.
Since the RF CP Gain bit is contained in the RF N Counter, only
one write is needed to both program a new output frequency and
also initiate Fastlock. To come out of Fastlock, the RF CP Gain bit
on the RF N register must be set to “0.” See Table VI.
APPLICATIONS SECTION
Local Oscillator for GSM Handset Receiver
Figure 7 shows the ADF4210/ADF4211/ADF4212/ADF4213
being used with a VCO to produce the LO for a GSM base
station transmitter.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50
. A typical GSM system
would have a 13 MHz TCXO driving the reference input with-
out any 50
termination. In order to have a channel spacing of
200 kHz (the GSM standard), the reference input must be
divided by 65, using the on-chip reference.
WIDEBAND PLL
Many of the wireless applications for synthesizers and VCOs in
PLLs are narrowband in nature. These applications include
various wireless standards such as GSM, DSC1800, CDMA, or
WCDMA. In each of these cases, the total tuning range for the
local oscillator is less than 100 MHz. However, there are also
wideband applications where the local oscillator could have up
to an octave tuning range. For example, cable TV tuners have
a total range of about 400 MHz. Figure 8 shows an applica-
tion where the ADF4213 is used to control and program the
Micronetics M3500–1324. The loop lter was designed for an
RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD
frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP
multiplied by the gain factor of 4), VCO KD of 80 MHz/V (sen-
sitivity of the M3500–1324 at an output of 2100 MHz) and a
phase margin of 45
°C.
In narrowband applications, there is generally a small variation
(less than 10%) in output frequency and also a small variation
(typically < 10%) in VCO sensitivity over the range. However,
100pF
51
VDD
VP
VDD2VDD1
ADF4210/
ADF4211/
ADF4212/
ADF4213
VP1
5.6k
620pF
3.3k
8.2nF
VCO190-
902T
VCC
18
100pF
18
RFOUT
REFIN
MUXOUT
LOCK
DETECT
100pF
AGND
IF
DGND
IF
RFIN
RFINB
CLK
DATA
LE
SPI-COMPATIBLE
SERIAL
BUS
DECOUPLING CAPACITORS (22 F/10PF) ON VDD, VP OF THE
ADF4211/ADF4212/ADF4213 AND ON VCC OF THE VCOS HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
RSET
CPRF
CPIF
1.3nF
18
100pF
18
IFOUT
100pF
VCO190-
540T
VCC
3.3k
2.7k
100pF
51
1000pF
FREFIN
51
1.3nF
5.6k
620pF
8.2nF
AGND
RF
DGND
RF
VP
VP2
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4210/ADF4211/ADF4212/ADF4213
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| ADF4212BRUZ-RL7 | 功能描述:IC PLL FREQ SYNTHESIZER 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4212L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Low Power PLL Frequency Synthesizer |
| ADF4212LBCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Low Power PLL Frequency Synthesizer |
| ADF4212LBCPZ | 功能描述:IC PLL FREQ SYNTHESIZER 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4212LBCPZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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