
PRELMNARY
DATA
SWALLOW
CO NTROL
TECHNCAL
a
Prelimnary Technical Data
ADF4206/ADF4207/ADF4208
FEATURES
ADF4206:
ADF4207:
ADF4208:
+2.7 V to +5.5 V Power Supply
Selectable Charge Pump Currents
Selectable Dual Modulus Prescaler
3-Wire Serial Interface
Power Down Mode
500MHz/500MHz
1.1GHz/1.1GHz
2.0GHz/1.1GHz
APPLICATIONS
Portable Wireless Communications (PCS/PCN, Cordless)
Cordless and Cellular Telephone Systems
Wireless Local Area Networks (WLANs)
Cable TV Tuners (CATV)
Pagers
GE NE RAL D E SC RIPT ION
T he ADF4206/ADF4207/ADF4208 is a dual frequency
synthesizer which can be used to implement local oscil-
lators in the up-conversion and down-conversion sec-
tions of wireless receivers and transmitters. T hey consist
of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference
modulus prescaler (P/P+1). T he A (6-bit) and B (11-
bit) counters, in conjunction with the dual modulus
prescaler (P/P+1), implement an N divider (N= BP+A).
In addition, the 14-bit reference counter (R Counter),
allows selectable REFIN frequencies at the PFD input.
A complete PLL (Phase-Locked Loop) can be imple-
mented if the synthesizers are used with an external loop
filter and VCO's (Voltage Controlled Oscillators)
Control of all the on-chip registers is via a simple 3-wire
interface.
power supply and can be powered down when not in
use.
Analog Devices, Inc., 1999
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781-329-4700
Fax: 781-326-8703
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of
Analog Devices.
Dual PLL Frequency Synthesizer
FUNCT IONAL BLOCK DIAGRAM
REV.PrD 07/99
RF2
IN
A
RF 2
PRESCALE R
CLOCK
DATA
LE
OSCILLATOR
22-BIT
DATA
REGISTER
IF
LOCK
DETECT
MUXOUT
CP
RF1
CP
RF2
CHARGE
PUMP
PHASE
CO MPARATOR
OUTPUT
MUX
+
-
17-BIT RF 2
N-COUNTER
14-BIT RF 2
R-COUNTER
OSCIN
RF 1
PRESCALE R
RF1
IN
A
CHARGE
PUMP
PHASE
CO MPARATOR
+
-
17-BIT RF 1
N-COUNTER
14-BIT RF 1
R-C OUNTER
SWALLOW
CONTRO L
V
DD
1
V
DD
2
V
P
1
V
P
2
AGND
RF1
DGND
RF1
DGND
RF2
AGND
RF2
RF
LOCK
DETECT
SDOUT
RF2
IN
B
RF1
IN
B
OSCOUT