參數(shù)資料
型號: ADF4157BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 24/24頁
文件大小: 0K
描述: IC PLL FREQ SYNTH 6GHZ 16TSSOP
標準包裝: 96
類型: 分數(shù) N 合成器(RF)
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 6GHz
除法器/乘法器: 是/是
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 551 (CN2011-ZH PDF)
配用: EVAL-ADF4157EB1Z-ND - BOARD EVALUATION FOR ADF4157
Data Sheet
ADF4157
Rev. D | Page 9 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
open. This ensures that there is no loading of the REFIN pin on
power-down.
BUFFER
TO R COUNTER
REFIN
100
k
NC
SW2
SW3
NC
SW1
POWER-DOWN
CONTROL
05874-
005
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by
a two-stage limiting amplifier to generate the current mode
logic (CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AVDD
2k
RFINB
RFINA
05874-
006
Figure 12. RF Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
25-BIT FIXED MODULUS
The ADF4157 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of
fRES = fPFD/225
where fPFD is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible.
INT, FRAC, AND R RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the RF
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RFOUT) equation is
RFOUT = fPFD × (INT + (FRAC/225))
(1)
where:
RFOUT is the output frequency of the external voltage controlled
oscillator (VCO).
INT is the preset divide ratio of the binary 12-bit counter (23 to
4095).
FRAC is the numerator of the fractional division (0 to 225 1).
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
T is the REFIN divide-by-2 bit (0 or 1).
RF R COUNTER
The 5-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 32 are allowed.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
05874-
007
Figure 13. RF N Divider
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