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參數(shù)資料
| 型號(hào)： | ADF4113HVBRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CHARGE PUMP HV SYNTH 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 4GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4113HVEB1Z-ND - BOARD EVALUATION FOR ADF4113HV EVAL-ADF4113EBZ2-ND - BOARD EVAL FOR ADF4113 1750MHZ EVAL-ADF4113EBZ1-ND - BOARD EVAL FOR ADF4113 EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP |
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Data Sheet
ADF4113HV
Rev. B | Page 15 of 20
APPLICATIONS
ADF4113HV
2.7k
VCO
GND
18
100pF
18
18
RFOUT
FREFIN
51
100pF
RFINA
RFINB
RSET
REFIN
CP
CE
CLK
DATA
LE
SPI-COMPATIBLE SERIAL BUS
MUXOUT
LOCK
DETECT
INPUT OUTPUT
2
14
6
5
1
8
LOOP
FILTER
NOTES
1. POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
AD5320
12-BIT
V-OUT DAC
06223-
023
Figure 23. Driving the RSET Pin with a Digital-to-Analog Converter
USING A DIGITIAL-TO-ANALOG CONVERTER TO
DRIVE THE RSET PIN
A digital-to-analog converter (DAC) can be used to drive the
RSET pin of the ADF4113HV, thus increasing the level of control
over the charge pump current (ICP). This can be advantageous in
wideband applications where the sensitivity of the VCO varies
over the tuning range. To compensate for this, ICP can be varied
to maintain good phase margin and ensure loop stability. See
Figure 23 for this configuration.
INTERFACING
The ADF4113HV has a simple SPI-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) goes high, the 24 bits that have
been clocked into the input register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 6 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device
is 833 kHz, or one update every 1.2 s. This rate is more than
adequate for systems that have typical lock times in the
hundreds of microseconds.
ADuC812 Interface
Figure 24 shows the interface between the ADF4113HV and the
ADuC812 MicroConverter. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4113HV needs
a 24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, the LE input should be brought high to
complete the transfer.
I/O port lines on the ADuC812 are also used to control power-
down (CE input), and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When the ADuC812 is operating in the SPI master mode, the
maximum SCLOCK rate of the ADuC812 is 4 MHz. This
means that the maximum rate at which the output frequency
can be changed is 166 kHz.
SCLOCK
MOSI
I/O PORTS
ADuC812
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4113HV
06223-
024
Figure 24. ADuC812 to ADF4113HV Interface
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4113HVBRUZ-RL7 | 功能描述:IC CHARGE PUMP HV SYNTH 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113HVSD1Z | 制造商:Analog Devices 功能描述:- Rail/Tube |
| ADF4116 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
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