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參數(shù)資料
| 型號： | ADF4111BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16-TSSOP |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP |
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Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 23 of 28
ADF4111
ADF4112
ADF4113
2.7k
VCO
GND
18
100pF
18
18
RFOUT
FREFIN
51
100pF
RFINA
RFINB
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
RSET
REFIN
CP
LOOP
FILTER
CE
CLK
DATA
LE
SPI COMPATIBLE SERIAL BUS
AD5320
12-BIT
V-OUT DAC
MUXOUT
LOCK
DETECT
INPUT OUTPUT
2
14
6
5
1
8
03496-0-039
Figure 34. Driving the RSET Pin with a D/A Converter
USING A D/A CONVERTER TO DRIVE THE RSET PIN
A D/A converter can be used to drive the RSET pin of the
ADF4110 family, thus increasing the level of control over the
charge pump current, ICP. This can be advantageous in wide-
band applications where the sensitivity of the VCO varies over
the tuning range. To compensate for this, the ICP may be varied
to maintain good phase margin and ensure loop stability. See
SHUTDOWN CIRCUIT
The attached circuit in Figure 35 shows how to shut down both
the ADF4110 family and the accompanying VCO. The ADG701
switch goes closed circuit when a Logic 1 is applied to the IN
input. The low cost switch is available in both SOT-23 and
MSOP packages.
WIDEBAND PLL
Many of the wireless applications for synthesizers and VCOs in
PLLs are narrow band in nature. These applications include the
various wireless standards like GSM, DSC1800, CDMA, and
WCDMA. In each of these cases, the total tuning range for the
local oscillator is less than 100 MHz. However, there are also
wideband applications for which the local oscillator could have
a tuning range as wide as an octave. For example, cable TV
tuners have a total range of about 400 MHz. Figure 36 shows an
application where the ADF4113 is used to control and program
the Micronetics M3500-2235. The loop filter was designed for
an RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD
frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP
multiplied by the gain factor of 4), VCO KD of 90 MHz/V
(sensitivity of the M3500-2235 at an output of 2900 MHz), and
a phase margin of 45°C.
In narrow-band applications, there is generally a small variation
in output frequency (generally less than 10%) and a small
variation in VCO sensitivity over the range (typically 10% to
15%). However, in wideband applications, both of these
parameters have a much greater variation. In Figure 36, for
example, there is a 25% and +17% variation in the RF output
from the nominal 2.9 GHz. The sensitivity of the VCO can vary
from 120 MHz/V at 2750 MHz to 75 MHz/V at 3400 MHz
(+33%, 17%). Variations in these parameters change the loop
bandwidth. This in turn can affect stability and lock time. By
changing the programmable ICP, it is possible to get compensa-
tion for these varying loop conditions and ensure that the loop
is always operating close to optimal conditions.
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| ADF4112BCPZ | 功能描述:IC PLL FREQ SYNTH 3GHZ 20-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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