參數(shù)資料
型號(hào)： ADF4002BCPZ-RL7
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： Phase Detector/Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 400 MHz, QCC20
封裝： ROHS COMPLIANT, MO-220VGGD-1, LFCSP-20
文件頁(yè)數(shù)： 9/24頁(yè)
文件大小： 336K
代理商： ADF4002BCPZ-RL7
ADF4002
Rev. 0 | Page 9 of 24
HI
HI
D1
D2
Q1
Q2
CLR1
CLR2
CP
U1
U2
UP
DOWN
ABP2
ABP1
CPGND
U3
R DIVIDER
PROGRAMMABLE
DELAY
N DIVIDER
V
P
CHARGE
PUMP
0
Figure 14. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4002 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 19 shows the full truth table. Figure 15 shows the
MUXOUT section in block diagram form.
DGND
DV
DD
CONTROL
MUX
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
0
Figure 15. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector (PD) cycles is less
than 15 ns. With LDP set to 1, five consecutive cycles of less
than 15 ns are required to set the lock detect. It stays set at high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle. For PFD frequencies greater than 10 MHz,
analog lock detect is more accurate because of the smaller pulse
widths.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected this output is high with narrow,
low-going pulses.
INPUT SHIFT REGISTER
The ADF4002 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 13-bit N counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB-first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in the timing diagram (see Figure 2). Table 6
provides the truth table for these bits. Figure 16 shows a
summary of how the latches are programmed.
Table 6. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
R Counter
0
1
N Counter
1
0
Function Latch
1
1
Initialization Latch
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