參數(shù)資料
型號： ADE7878ACPZ
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁數(shù)： 80/96頁
文件大?。?/td> 1096K
代理商： ADE7878ACPZ
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E| Page 81 of 96
Bit
Location
Bit Mnemonic
Default Value
Description
6
REVAPA
0
When this bit is set to 1, it indicates that the Phase A active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 47).
7
REVAPB
0
When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 47).
8
REVAPC
0
When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 47).
9
REVPSUM1
0
When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 datapath
has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN register
(see Table 47).
10
REVRPA
0
When this bit is set to 1, it indicates that the Phase A reactive power identified by Bit 7
(REVRPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 4 (AVARSIGN) of the PHSIGN register (see Table 47). This bit is
always 0 for ADE7854.
11
REVRPB
0
When this bit is set to 1, it indicates that the Phase B reactive power identified by Bit 7
(REVRPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 5 (BVARSIGN) of the PHSIGN register (see Table 47). This bit is
always 0 for ADE7854.
12
REVRPC
0
When this bit is set to 1, it indicates that the Phase C reactive power identified by Bit 7
(REVRPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 6 (CVARSIGN) of the PHSIGN register (see Table 47). This bit is
always 0 for ADE7854.
13
REVPSUM2
0
When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 datapath
has changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN register
(see Table 47).
14
CF1
When this bit is set to 1, it indicates a high to low transition has occurred at CF1 pin; that
is, an active low pulse has been generated. The bit is set even if the CF1 output is disabled
by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power used at the CF1
pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register (see Table 45).
15
CF2
When this bit is set to 1, it indicates a high-to-low transition has occurred at the CF2 pin;
that is, an active low pulse has been generated. The bit is set even if the CF2 output is
disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power used at
the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 45).
16
CF3
When this bit is set to 1, it indicates a high-to-low transition has occurred at CF3 pin; that
is, an active low pulse has been generated. The bit is set even if the CF3 output is disabled
by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power used at the CF3
pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 45).
17
DREADY
0
When this bit is set to 1, it indicates that all periodical (at 8 kHz rate) DSP computations
have finished.
18
REVPSUM3
0
When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 datapath
has changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN register
(see Table 47).
31:19
Reserved
0 0000 0000 0000
Reserved. These bits are always 0.
Table 38. STATUS1 Register (Address 0xE503)
Bit
Location
Bit Mnemonic
Default Value
Description
0
NLOAD
0
When this bit is set to 1, it indicates that at least one phase entered no load condition based
on total active and reactive powers. The phase is indicated in Bits[2:0] (NLPHASE[x]) in the
PHNOLOAD register (see Table 42).
1
FNLOAD
0
When this bit is set to 1, it indicates that at least one phase entered no load condition based
on fundamental active and reactive powers. The phase is indicated in Bits[5:3] (FNLPHASE[x])
in PHNOLOAD register (see Table 42 in which this register is described). This bit is always 0
for ADE7854, ADE7858, and ADE7868.
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