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參數(shù)資料
| 型號： | ADDC02808 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Pulsed DC/ DC Converter with Integral EMI Filter(帶積分EMI濾波器的DC-DC轉(zhuǎn)換器) |
| 中文描述： | 脈沖直流/直流轉(zhuǎn)換器積分EMI過濾器（帶積分的EMI濾波器的的DC - DC轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 295K |
| 代理商： | ADDC02808 |
ADDC02808PB
REV. A
–9–
8.1
7.4
–200
800
–100
V
O
0
100
200
300
400
500
600
700
8
7.9
7.8
7.7
7.6
7.5
TIME –
m
s
Figure 21. Predicted Response for 24 A Step Load
Change in Load Current, di/dt = 12 A/
μ
s, for C
LOAD
=
2,000
μ
F and R
ESR
= 5 m
8.1
7.4
–200
800
–100
0
100
200
300
400
500
600
700
8
7.9
7.8
7.7
7.6
7.5
V
O
TIME –
m
s
Figure 22. Predicted Response for 24 A Step Load
Change in Load Current, di/dt = 12 A/
μ
s, for C
LOAD
=
4,000
μ
F and R
ESR
= 2.5 m
Factory Set Internal Compensation
If the user knows the external load capacitance and R
ESR
to be
used in the application and if the application requires better
pulse response than is summarized in Table I, then the internal
feedback compensation can be modified at the factory to im-
prove the transient response. In these instances, the compensa-
tion is optimized for a particular C
LOAD
at the expense of
performing well over a broader range of C
LOAD
. The predicted
maximum output voltage deviation and settling times for fac-
tory-modified feedback compensation are shown in Figures 23,
24, and 25, and summarized in Table II, for three combinations
of C
LOAD
and R
ESR
. As can be seen, optimizing the compensa-
tion for a given load capacitance gives the best transient re-
sponse in terms of both voltage deviation and settling time.
Table II.
Output Response to a 24 A (1 A-25 A) Step in
Load Current (Compensation Optimized)
Typical
Deviation
Settling Time
(Within 1%)
125
μ
s
100
μ
s
0
μ
s
See
Figure
C
LOAD
1,000
μ
F
2,000
μ
F
4,000
μ
F
R
ESR
10 m
5 m
2.5 m
–4%
–2.5%
–1%
23
24
25
Connection to Load
Pulse performance is dependent on minimizing the parasitic
impedances in the connection between the converter output and
the load and external capacitors. Low inductance and low resis-
tance connections should be used. Multilayer connections should
be avoided to minimize stray capacitance. The converter should
be placed as close to the load and external capacitors as possible.
8.1
7.4
–200
800
–100
V
O
0
100
200
300
400
500
600
700
8
7.9
7.8
7.7
7.6
7.5
TIME –
m
s
Figure 23. Predicted Response for 24 A Step Load Change,
di/dt = 12 A/
μ
s, with Factory Set Internal Compensation
Optimized for C
LOAD
= 1,000
μ
F and R
ESR
= 10 m
8.1
7.4
–200
800
–100
V
O
0
100
200
300
400
500
600
700
8
7.9
7.8
7.7
7.6
7.5
TIME –
m
s
Figure 24. Predicted Response for 24 A Step Load Change,
di/dt = 12 A/
μ
s, with Factory Set Internal Compensation
Optimized for C
LOAD
= 2,000
μ
F and R
ESR
= 5 m
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