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參數(shù)資料
| 型號： | ADCS7478AIMFX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 1MSPS, 12-/10-/8-Bit A/D Converters in 6-Lead SOT-23 |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | SOT-23, 6 PIN |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 514K |
| 代理商： | ADCS7478AIMFX |
Applications Information
(Continued)
4.0 SAMPLE CIRCUIT
A typical application of the ADCS7476/77/78 is shown in
Figure 8. The combined analog and digital supplies are
provided in this example by the National LP2950 low-
dropout voltage regulator, available in a variety of fixed and
adjustable output voltages. The supply is bypassed with a
capacitor network located close to the device. The three-wire
interface is also shown connected to a microprocessor or
DSP.
5.0 ANALOG INPUTS
An equivalent circuit for the ADCS7476/77/78 input channel
is shown in Figure 9. The diodes D1 and D2 provide ESD
protection for the analog inputs. At no time should an analog
input exceed V
DD
+ 300 mV or GND - 300 mV, as these ESD
diodes will begin conducting current into the substrate and
affect ADC operation.
The capacitor C1 in Figure 9 typically has a value of 4 pF,
and is mainly due to pin capacitance. The resistor R1 repre-
sents the on resistance of the multiplexer and track / hold
switch, and is typically 100 ohms. The capacitor C2 is the
ADCS7476/77/78 sampling capacitor, and is typically 26 pF.
The sampling nature of the analog input causes input current
pulses that result in voltage spikes at the input. The
ADCS7476/77/78 will deliver best performance when driven
by a low-impedance source to eliminate distortion caused by
the charging of the sampling capacitance. In applications
where dynamic performance is critical, the input might need
to be driven with a low output-impedance amplifier. In addi-
tion, when using theADCS7476/77/78 to sampleAC signals,
a band-pass or low-pass filter will reduce harmonics and
noise and thus improve THD and SNR.
6.0 DIGITAL INPUTS AND OUTPUTS
The ADCS7476/77/78 digital inputs (SCLK and CS) are not
limited by the same absolute maximum ratings as the analog
inputs. The digital input pins are instead limited to +6.5V with
respect to GND, regardless of V
DD
, the supply voltage. This
allows the ADCS7476/77/78 to be interfaced with a wide
range of logic levels, independent of the supply voltage.
Note that, even though the digital inputs are tolerant of up to
+6.5V above GND, the digital outputs are only capable of
driving V
out. In addition, the digital input pins are not
prone to latch-up; SCLK and CS may be asserted before
V
DD
without any risk.
7.0 MODES OF OPERATION
The ADCS7476/77/78 has two possible modes of operation:
normal mode, and shutdown mode. The ADCS7476/77/78
enters normal mode (and a conversion process is begun)
when CS is pulled low. The device will enter shutdown mode
if CS is pulled high before the tenth falling edge of SCLK
after CS is pulled low, or will stay in normal mode if CS
remains low. Once in shutdown mode, the device will stay
there until CS is brought low again. By varying the ratio of
time spent in the normal and shutdown modes, a system
may trade-off throughput for power consumption.
8.0 NORMAL MODE
The best possible throughput is obtained by leaving the
ADCS7476/77/78 in normal mode at all times, so there are
no power-up delays. To keep the device in normal mode
continuously, CS must be kept low until after the 10th falling
edge of SCLK after the start of a conversion (remember that
a conversion is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before
the 16th falling edge, the device will remain in normal mode,
but the current conversion will be aborted, and SDATA will
return to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion
word from the device. After sixteen SCLK cycles have
elapsed, CS may be idled either high or low until the next
conversion. If CS is idled low, it must be brought high again
before the start of the next conversion, which begins when
CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE.
Another conversion may be started, after t
QUIET
has
elapsed, by bringing CS low again.
9.0 SHUTDOWN MODE
Shutdown mode is appropriate for applications that either do
not sample continuously, or are willing to trade throughput
for power consumption. When the ADCS7476/77/78 is in
shutdown mode, all of the analog circuitry is turned off.
To enter shutdown mode, a conversion must be interrupted
by bringing CS back high anytime between the second and
tenth falling edges of SCLK, as shown in Figure 10. Once CS
has been brought high in this manner, the device will enter
shutdown mode; the current conversion will be aborted and
SDATAwill enter TRI-STATE. If CS is brought high before the
second falling edge of SCLK, the device will not change
mode; this is to avoid accidentally changing mode as a result
of noise on the CS line.
20057713
FIGURE 8. Sample Circuit
20057714
FIGURE 9. Equivalent Input Circuit
A
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADCS7478AIMFX/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADCS7478AISDX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP |
| ADCS9888 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End |
| ADCS9888_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End |
| ADCS9888C WAF | 制造商:Texas Instruments 功能描述: |
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