參數(shù)資料
型號(hào): ADCS7478
廠(chǎng)商: National Semiconductor Corporation
元件分類(lèi): 串行ADC
英文描述: 1MSPS, 12-/10-/8-Bit A/D Converters in 6-Lead SOT-23
中文描述: 1MSPS,12/10/8位的A / D轉(zhuǎn)換器采用6引腳SOT - 23
文件頁(yè)數(shù): 9/22頁(yè)
文件大小: 514K
代理商: ADCS7478
Timing Test Circuit
20057708
ADCS7476/ADCS7477/ADCS7478 Timing Specifications
The following specifications apply for V
= +2.7V to 5.25V, f
SCLK
= 20 MHz,
Boldface limits apply for T
A
= 40C to +85C
:
all other limits T
A
= 25C, unless otherwise noted. (Note 9)
Symbol
Parameter
Conditions
t
CONVERT
t
QUIET
(Note 5)
t
1
Minimum CS Pulse Width
t
2
CS to SCLK Setup Time
Delay from CS Until SDATA
TRI-STATE
Disabled (Note 6)
Data Access Time after SCLK Falling
Edge(Note 7)
V
DD
= +4.75 to +5.25
Typical
16 x t
SCLK
Limits
Units
50
10
10
ns (min)
ns (min)
ns (min)
t
3
20
ns (max)
t
4
V
DD
= +2.7 to +3.6
40
20
ns (max)
ns (max)
t
5
SCLK Low Pulse Width
0.4 x
t
SCLK
0.4 x
t
SCLK
7
5
25
6
25
5
ns (min)
t
6
SCLK High Pulse Width
ns (min)
t
7
SCLK to Data Valid Hold Time
V
DD
= +2.7 to +3.6
V
DD
= +4.75 to +5.25
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
t
8
SCLK Falling Edge to SDATA High
Impedance (Note 8)
V
DD
= +2.7 to +3.6
V
DD
= +4.75 to +5.25
t
POWER-UP
Power-Up Time from Full
Power-Down
1
μs
Note 5:
Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion
Note 6:
Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.
Note 7:
Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.
Note 8:
t
8
is derived from the time taken by the outputs to change by 0.5V with the loading circuit shown above. The measured number is then adjusted to remove
the effects of charging or discharging the 25pF capacitor. This means t
8
is the true bus relinquish time, independent of the bus loading.
Note 9:
All input signals are specified as t
r
= t
f
= 5 ns (10% to 90% V
DD
) and timed from 1.6V.
A
www.national.com
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