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參數(shù)資料
型號(hào)： ADCMP581BCPZ-R2
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/16頁(yè)
文件大?。?/td> 0K
描述： IC COMPARATOR ECL UFAST 16-LFCSP
標(biāo)準(zhǔn)包裝： 250
類型： 帶鎖銷
元件數(shù)： 1
輸出類型： 補(bǔ)充型，ECL
電壓 - 電源，單路/雙路(±)： ±4.5 V ~ 5.5 V
電壓 - 輸入偏移（最小值）： 10mV @ ±5V
電流 - 輸入偏壓（最小值）： 30µA @ ±5V
電流 - 輸出（標(biāo)準(zhǔn)）： 44mA @ 5V
電流 - 靜態(tài)（最大值）： 8mA
CMRR, PSRR（標(biāo)準(zhǔn)）： 60dB CMRR，75dB PSRR
傳輸延遲（最大）： 0.18ns
磁滯： 1mV
工作溫度： -40°C ~ 125°C
封裝/外殼： 16-VFQFN 裸露焊盤，CSP
安裝類型： 表面貼裝
包裝： 帶卷 (TR)
配用： EVAL-ADCMP581BCPZ-ND - BOARD EVALUATION ADCMP581BCP
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Q
LE
PIN 1
INDICATOR
1
VTP
2
VP
3
VN
4
VTN
11 Q
12 GND
10
9GND
5
V
C
I
6
7
L
E
8
V
T
15
G
N
D
16
V
C
I
14
H
Y
S
13
V
E
ADCMP580
TOP VIEW
(Not to Scale)
0
46
72
-00
3
Figure 3. ADCMP580 Pin Configuration
Q
LE
PIN 1
INDICATOR
1
VTP
2
VP
3
VN
4
VTN
11 Q
12 GND
10
9GND
5
V
C
I
6
7
L
E
8
V
T
15
G
N
D
16
V
C
I
14
H
Y
S
13
V
E
ADCMP581
TOP VIEW
(Not to Scale)
0
46
72
-00
4
Figure 4. ADCMP581 Pin Configuration
Q
LE
PIN 1
INDICATOR
1
VTP
2
VP
3
VN
4
VTN
11 Q
12 VCCO
10
9VCCO
5
V
C
I
6
7
L
E
8
V
T
15
G
N
D
16
V
C
I
14
H
Y
S
13
V
E
ADCMP582
TOP VIEW
(Not to Scale)
0
46
72
-00
5
Figure 5. ADCMP582 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VTP
Termination Resistor Return Pin for VP Input.
2
VP
Noninverting Analog Input.
3
VN
Inverting Analog Input.
4
VTN
Termination Resistor Return Pin for VN Input.
5, 16
VCCI
Positive Supply Voltage.
6
LE
Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of
the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being
placed into latch mode. LE must be driven in complement with LE.
7
LE
Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the
input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the
comparator being placed into latch mode. LE must be driven in complement with LE.
8
VTT
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP580 (CML output stage), this pin should be connected to the GND ground.
For the ADCMP581 (ECL output stage), this pin should be connected to the –2 V termination potential.
For the ADCMP582 (PECL output stage), this pin should be connected to the VCCO – 2 V termination potential.
9, 12
GND/VCCO
Digital Ground Pin/Positive Logic Power Supply Terminal.
For the ADCMP580/ADCMP581, this pin should be connected to the GND pin.
For the ADCMP582, this pin should be connected to the positive logic power VCCO supply.
10
Q
Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog
voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions
(Pin 6 to Pin 7) for more information.
11
Q
Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE
descriptions (Pin 6 to Pin 7) for more information.
13
VEE
Negative Power Supply.
14
HYS
Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing of the HYS
hysteresis control resistor.
15
GND
Analog Ground.
Heat Sink
Paddle
N/C
The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left
floating for optimal electrical isolation between the package handle and the substrate of the die. It can also
be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal
at package corners is connected to the heat sink paddle.
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