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參數(shù)資料
| 型號(hào)： | ADCLK948/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADCLK948 |
| 設(shè)計(jì)資源： | ADCLK948 Eval Brd Schematic ADCLK948 Gerber Files ADCLK948 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SIGe |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘緩沖器 / 驅(qū)動(dòng)器 / 接收器 / 變換器 |
| 已用 IC / 零件： | ADCLK948 |
| 主要屬性： | 2 個(gè)可選輸入，8 輸出 |
| 次要屬性： | LVPECL 輸出邏輯 |
| 已供物品： | 板 |
Two Selectable Inputs, 8 LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK948
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2009–2010 Analog Devices, Inc. All rights reserved.
FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK948 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The ADCLK948 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The ADCLK948 features eight full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The ADCLK948 features eight full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC 2 V for a total differential
output swing of 1.6 V.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC 2 V for a total differential
output swing of 1.6 V.
The ADCLK948 is available in a 32-lead LFCSP and specified
for operation over the standard industrial temperature range of
40°C to +85°C.
The ADCLK948 is available in a 32-lead LFCSP and specified
for operation over the standard industrial temperature range of
40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
VT0
VREF0
VREF1
IN_SEL
CLK0
VT1
CLK1
LVPECL
ADCLK948
REFERENCE
08
28
0-
0
01
Figure 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCLK950 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer |
| ADCLK950/PCBZ | 功能描述:BOARD EVALUATION FOR ADCLK950 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SIGe 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| ADCLK950BCPZ | 功能描述:IC CLOCK BUFFER MUX 2:10 40LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:SIGe 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ADCLK950BCPZ-REEL7 | 功能描述:IC CLOCK BUFFER MUX 2:10 40LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:SIGe 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ADCLK954 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer |
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