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參數(shù)資料
| 型號： | ADC16471CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 355K |
| 代理商： | ADC16471CIWM |
TL/H/11454–7
FIGURE 5. Timing Diagrams for Data Output Enable (DOE) and Serial Data Out (SDO)
Pin Description
V
REF
a
, V
REF
b
These are the ADC16471’s internal differ-
ential reference’s bypass pins. Their nomi-
nal output voltage is
around the voltage at the V
MID
pin, typically
V
A
a
/2. V
REF
a
, V
MID
, and V
REF
b
should
be bypassed with a parallel combination of
10
m
F and 0.1
m
F capacitors. For the
ADC16071, these are the reference voltage
inputs. V
REF
a
and V
MID
should be by-
passed with a parallel combination of 10
m
F
and 0.1
m
F capacitors.
V
MID
This pin is the internal differential refer-
ence’s V
A
a
/2 output pin. V
MID
should be
bypassed with a parallel combination of
10
m
F and 0.1
m
F capacitors.
V
IN
a
, V
IN
b
These are the ADC’s differential input pins.
Signals applied to these pins can be single-
ended or differential with respect to the
V
MID
voltage.
PD
This is the input pin used to activate the
power-down mode. When a logic LOW (0)
is applied to this pin the supply current
drops from 100 mA (max) to 1.3 mA (max).
g
1.25V centered
AGND
This is the connection to system analog
ground. Internally, this ground is connected
to the analog circuitry, including the fourth-
order modulator.
DGND
This is the connection to system digital
ground. Internally, this ground is connected
to all digital circuitry except the modulator’s
clock.
MGND
This is the ground pin for the modulator’s
clock. It should be connected to analog
ground through its own connection that is
separate from that used by AGND.
V
A
a
This pin is the connection to the system an-
alog voltage supply. Best performance is
achieved when this pin is bypassed with a
parallel combination of 10
m
F and 0.1
m
F
capacitors.
V
M
a
This is the modulator’s supply pin. V
M
a
should
be connected to the system analog voltage
supply with a circuit board trace or connection
that is separate from that used to supply V
A
a
.
Best performance is achieved when this pin is
bypassed with a parallel combination of 10
m
F
and 0.1
m
F capacitors.
This pin is the connection to the system digital
voltage supply. Best performance is achieved
when this pin is bypassed with a parallel combi-
nation of 10
m
F and 0.1
m
F capacitors.
This is the Serial Format pin. The logic level
applied to the
SFMT
pin determines whether
conversion data shifted out of the
SDO
pin is
valid on the rising or falling edge of
SCO
. It also
controls the format of the Frame Sync Out
(FSO)
signal. See the
Serial Interface
section
for details.
V
D
a
SFMT
TM0, TM1
Used to enabled test mode during production.
Connect both pins to DGND.
FSI
This is the Frame Sync Input pin.
FSI
is an
input used to synchronize the ADC16071/
ADC16471’s conversions to an external source.
The state of
FSI
is sampled on the falling edge
of
CLK
. See the
Serial Interface
section for
details.
CLK
This is the clock signal input pin. The signal ap-
plied to this pin sets the sample rate of the
ADC16071/ADC16471’s modulator to f
CLK
/2.
The frequency range can be 1 MHz
s
f
CLK
s
25 MHz.
SCO
This is the Serial Clock Output pin. The
ADC16071/ADC16471’s serial data transmis-
sion is synchronous with the
SCO
signal.
SCO
has a frequency of f
CLK
/4. See the
Serial In-
terface
section for details.
SDO
This is the Serial Data Output pin. The
ADC16071/ADC16471’s conversion data is
shifted out from this pin synchronous to the
SCO
signal. See the
Serial Interface
section
for details.
12
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