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參數(shù)資料
| 型號： | ADC14161 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low Dropout Linear 2-cell Li-Ion Charge Controller with AutoCompTM, 8.4V 8-SOIC -20 to 70 |
| 中文描述： | 低失真，自校準14位，250 MSPS的，390毫瓦的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 471K |
| 代理商： | ADC14161 |
Functional Description
Operating on a single +5V supply, the ADC14161 uses a
pipelined architecture and has error correction circuitry and a
calibration mode to help ensure maximum performance at all
times.
Balanced analog signals with a peak-to-peak voltage equal
to the input reference voltage, V
REF
, and centered around
the common mode input voltage, V
, are digitized to 14 bits
(13 bits plus sign). Neglecting offsets, positive input signal
voltages (V
+ V
>
0) produce positive digital output
data and negative input signal voltages (V
+ V
<
0)
produce negative output data. The input signal can be digi-
tized at any clock rate between 300 Ksps and 2.5 Msps.
Input voltages below the negative full scale value will cause
the output word to take on the negative full scale value of
10,0000,0000,0000. Input voltage above the positive full
scale value will cause the output word to take on the positive
full scale value of 01,1111,1111,1111.
The output word rate is the same as the clock frequency. The
analog input voltage is acquired at the falling edge of the
clock and the digital data for that sample is delayed by the
pipeline for 13 clock cycles plus t
. The digital out-
put is undefined if the chip is being reset or is in the calibra-
tion mode. The output signal may be inhibited by the RD pin
while the converter is in one of these modes.
The RD pin must be low to enable the digital outputs. A logic
low on the power down (PD) pin reduces the converter
power consumption to less than two milliwatts.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC14161:
4.75V
≤
V
A
≤
5.25V
5.25V
≤
V
D
≤
5.25V
3.0V
≤
V
D
I/O
≤
VD
0.3MHz
≤
f
CLK
≤
2.5 MHz
V
CM
= 2.0V (forced)
V
REF IN
+ = 2.0V
V
REF IN
= AGND
1.1 The Analog Inputs
TheADC14161 has two analog signal inputs, V
+ and V
.
These two pins form a balanced signal input. There are two
reference pins, V
+
and V
REF
IN
. These pins form a
differential input reference.
1.2 Reference Inputs
V
+
should always be more positive than V
. The
effective reference voltage, V
REF
, is the difference between
these two voltages:
V
REF
= (V
REF
+
IN
) (V
REF
IN
).
The operational voltage range of V
+
is +1.8 Volts to
+3.0 Volts. The operational voltage range of V
is
ground to 1.0V. For best performance, the difference be-
tween V
REF
+
IN
and V
REF
IN
should remain within the range
of 1.8V to 2.2V. Reducing the reference voltage below 1.8V
will decrease the signal-to-noise ratio (SNR) of the
ADC14161. Increasing the reference voltage (and, conse-
quently, the input signal swing) above 2.2V will increase
THD.
V
REF (MID)
is the reference mid-point and is derived from
V
CM
. This point is brought out only to be by passed. By pass
this pin with 0.1μF capacitor to ground. Do not load this pin.
It is very important that all grounds associated with the refer-
ence voltage make connection to the analog ground plane at
a single point to minimize the effects of noise currents in the
gound path.
1.3 Signal Inputs
The signal inputs are V
IN
+ and V
IN
. The signal input, V
IN
,
is defined as
V
IN
= (V
IN
+) (V
IN
).
Figure 3 indicates the relationship between the input voltage
and the reference voltages. Figure 4 shows the expected in-
put signal range.
The ADC14161 performs best with a balanced input cen-
tered around V
. The peak-to-peak voltage swing at either
V
+ or V
should be less than the reference voltage and
each signal input pin should be centered on the V
voltage.
The two V
-centered input signals should be exactly 180
out of phase from each other. As a simple check to ensure
this, be certain that the average voltage at the ADC iinput
pins is equal to V
. Drive the analog inputs with a source
impedance less than 100 Ohms.
DS100154-17
FIGURE 3. Typical Input to Reference Relationaship.
DS100154-18
FIGURE 4. Expected Input Signal Range.
A
www.national.com
13
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