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參數(shù)資料
| 型號： | ADC14071 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 14-Bit, 7 MSPS, 380 mW A/D Converter |
| 中文描述： | 14位，7 MSPS的，380毫瓦的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 427K |
| 代理商： | ADC14071 |
Applications Information
(Continued)
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pin should be bypassed with a 10 μF ca-
pacitor and with a 0.1 μF ceramic chip capacitor a centimeter
of each power pin. Leadless chip capacitors are preferred
because they provide low lead inductance.
As is the case with all high-speed converters, the ADC14071
is sensitive to power supply noise. Accordingly the noise on
the analog supply pin should be kept below 10 mV
P-P
.
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be espe-
cially careful of this during power up.
The DR V
pin provides power for the output drivers and
may be operated from a supply in the range of 2.7V to the V
D
supply (nominal 5V). This can simplify interfacing to 3.0V de-
vices and systems. Powering the DR V
from 3V will also re-
duce power consumption and noise generation due to output
switching.
DO NOT operate the DR V
D
pin at a voltage
higher than V
D
.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. Separate analog and
digital ground planes that are connected close to the
ADC14071 are required to achieve specified performance.
The analog and digital grounds may be in the same layer, but
should be separated from each other and should never over-
lap each other. Separation should be at least
1
8
inch (3 mm),
where possible.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should not be connected to system ground in close proximity
to any of the ADC14071’s other ground pins.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance. The solution is to keep the analog cir-
cuitry separated from the digital circuitry and from the digital
ground plane, as well as to keep the clock line as short as
possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signifi-
cant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or sig-
nal edges, like the 74F and the 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is very narrow compared with the
rest of the ground plane. A typical width is about 1/16 inch
(1.5 mm to 2 mm) but will depend upon the total analog
ground current that will flow through it. This narrowing pro-
vides a fairly high impedance to the high edge rates of the
digital switching currents, directing them away from the ana-
log pins. The lower slew rate analog ground currents see a
DS101101-27
FIGURE 7. Driving the Signal Inputs with a Transformer
A
www.national.com
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| ADC1410S065F2-DB | 功能描述:ADC1410S065 - 14 Bit 65M Samples per Second Analog to Digital Converter (ADC) Evaluation Board 制造商:idt, integrated device technology inc 系列:- 零件狀態(tài):過期 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):14 采樣率（每秒）:65M 數(shù)據(jù)接口:SPI 輸入范圍:2 Vpp 不同條件下的功率（典型值）:380mW @ 65MSPS 使用的 IC/零件:ADC1410S065 所含物品:板 標準包裝:1 |
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