- 您現在的位置：買賣IC網 > PDF目錄378284 > ADC12H030 (National Semiconductor Corporation) Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold(可自行校對12位串行輸入/輸出帶MUX，采樣/保持功能A/D轉換器) PDF資料下載
參數資料
| 型號： | ADC12H030 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold(可自行校對12位串行輸入/輸出帶MUX，采樣/保持功能A/D轉換器) |
| 中文描述： | 自校準12位帶符號串行I /辦公自動化/ D轉換器MUX和采樣/保持（可自行校對12位串行輸入/輸出帶復用，采樣/保持功能的A / D轉換器） |
| 文件頁數： | 29/41頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | ADC12H030 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
Application Hints
(Continued)
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects. Not do-
ing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below de-
tails out the number of clock periods required for different
DO formats:
Number of
SCLKs
Expected
8
9
12
13
16
17
DO Format
8-Bit MSB or LSB First
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
12-Bit MSB or LSB First
16-Bit MSB or LSB first
If erroneous SCLK pulses desynchronize the communica-
tions, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.
The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continu-
ously vs the case when CS is cycled. Take the I/O sequence
detailed in Figure 7 (Typical Power Supply Sequence) as an
example. The table below lists the number of SCLK pulses
required for each instruction:
Instruction
CS Low
Continuously
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
CS Strobed
Auto Cal
Read Status
Read Status
12-Bit + Sign Conv 1
12-Bit + Sign Conv 2
8 SCLKs
8 SCLKs
8 SCLKs
8 SCLKs
13 SCLKs
1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
for a particular A/D conversion (see Tables 2, 3, 4 and Table
5). In Figure 8the only times when the channel configuration
could be modified would be during I/O sequences 1, 4, 5 and
6. Input channels are reselected before the start of each new
conversion. Shown below is the data bit stream required on
DI, during I/O sequence number 4 in Figure 8 to set CH1 as
the positive input and CH0 as the negative input for the dif-
ferent versions of ADCs:
Part
Number
ADC12H030
ADC12030
ADC12H032
ADC12032
ADC12H034
ADC12034
ADC12H038
ADC12038
DI Data
DI3
L
DI0
L
DI1
H
DI2
L
DI4
H
DI5
L
DI6
X
DI7
X
L
H
L
L
H
L
X
X
L
H
L
L
L
H
L
X
L
H
L
L
L
L
H
L
Where X can be a logic high (H) or low (L).
1.5 Power Up/Down
The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see Tables 5,
6 and the Power Up/Down timing diagrams). When the ADC
is powered down in this way, the circuitry necessary for an
A/D conversion is deactivated. The circuitry necessary for
digital I/O is kept active. Hardware power up/down is con-
trolled by the state of the PD pin. Software power-up/down is
controlled by the instruction issued to the ADC. If a software
power up instruction is issued to the ADC while a hardware
power down is in effect (PD pin high) the device will remain
in the power-down state. If a software power down instruc-
tion is issued to the ADC while a hardware power up is in ef-
fect (PD pin low), the device will power down. When the de-
vice is powered down by software, it may be powered up by
either issuing a software power up instruction or by taking
PD pin high and then low. If the power down command is is-
sued during an A/D conversion, that conversion is disrupted.
Therefore, the data output after power up cannot be relied
upon.
DS011354-37
FIGURE 8. Changing the ADC’s Conversion Configuration
www.national.com
29
相關PDF資料 |
PDF描述 |
|---|---|
| ADC12030 | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| ADC12032 | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| ADC12034 | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| ADC12038 | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| ADC1230 | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADC12H030CIWM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| ADC12H030CIWM/NOPB | 功能描述:IC ADC 12BIT W/S&H +SIGN 16SOIC RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| ADC12H030CIWMX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
| ADC12H032 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| ADC12H032CIWM | 功能描述:IC ADC 12BIT 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
發(fā)布緊急采購，3分鐘左右您將得到回復。