參數(shù)資料
型號(hào)： ADC12762CCV
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： Low Dropout Linear 1-cell Li-Ion Charge Controller with AutoCompTM, 4.2V 8-MSOP -20 to 70
中文描述： 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 3/20頁(yè)
文件大小： 427K
代理商： ADC12762CCV
DC Electrical Characteristics
The following specifications apply for DV
= AV
= +5V, V
= +4.096V, V
REF(SENSE)
= AGND, and f
s
=
1.4 MHz, unless otherwise specified.
Boldface limits apply for T
A
= T
J
from T
MIN
to T
MAX
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typ
Limit
(Note 8)
2.0
0.8
1.0
1.0
Units
(Limit)
V (min)
V (max)
μA (max)
μA (max)
(Note 7)
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
DV
CC
= AV
CC
= +5.5V
DV
CC
= AV
CC
= +4.5V
0.1
0.1
V
OUT(1)
Logical “1” Output Voltage
DV
CC
= AV
CC
= +4.5V,
I
OUT
= 360 μA
I
OUT
= 100 μA
DV
CC
= AV
CC
= +4.5V,
I
OUT
= 1.6 mA
2.4
4.25
V (min)
V (min)
V
OUT(0)
Logical “0” Output Voltage
0.4
V (max)
I
OUT
TRI-STATE
Output
Leakage Current
TRI-STATE Output Capacitance
Digital Input Capacitance
DV
CC
Supply Current
AV
CC
Supply Current
Standby Current (DI
CC
+ AI
CC
)
Pins DB0–DB11
0.1
3
μA (max)
C
OUT
C
IN
DI
CC
AI
CC
I
STANDBY
Pins DB0–DB11
5
4
2
32
50
pF
pF
10
50
mA (max)
mA (max)
μA
PD = 0V
AC Electrical Characteristics
The following specifications apply for DV
= AV
= +5V, V
= +4.096V, V
REF(SENSE)
= AGND, and f
s
=
1.4 MHz, unless otherwise specified.
Boldface limits apply for T
A
= T
J
from T
MIN
to T
MAX
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typ
Limit
(Note 8)
Units
(Limits)
(Note 7)
f
s
Maximum Sampling Rate
(1/t
THROUGHPUT
)
Conversion Time
(S/H Low to EOC High)
Aperture Delay
(S/H Low to Input Voltage Held)
1.5
MHz (min)
t
CONV
593
560
710
ns (min)
ns (max)
t
AD
20
ns
t
S/H
S/H Pulse Width
10
5
ns (min)
ns (max)
ns (min)
ns (max)
400
60
126
t
EOC
S/H Low to EOC Low
90
t
ACC
Access Time
(RD Low or OE High to Data Valid)
TRI-STATE Control
(RD High or OE Low to Databus TRI-STATE)
Delay from RD Low to INT High
C
L
= 100 pF
10
20
ns (max)
t
1H
, t
0H
R
L
= 1k, C
L
= 10 pF
25
40
ns (max)
t
INTH
C
L
= 100 pF
35
60
35
10
15
ns (max)
ns (min)
ns (max)
ns (max)
t
INTL
Delay from EOC High to INT Low
C
L
= 100 pF
25
t
UPDATE
EOC High to New Data Valid
Multiplexer Address Setup Time
(MUX Address Valid to EOC Low)
Multiplexer Address Hold Time
(EOC Low to MUX Address Invalid)
CS Setup Time
(CS Low to RD Low, S/H Low, or OE High)
5
t
MS
50
ns (min)
t
MH
50
ns (min)
t
CSS
20
ns (min)
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