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參數(shù)資料
| 型號： | ADC12662CIVF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 495K |
| 代理商： | ADC12662CIVF |
Applications Information
(Continued)
3.0 ANALOG MULTIPLEXER
The ADC12662 has an input multiplexer that is controlled by
the logic level on pin S0 when EOC goes low, as shown in
Figure 1and 2.Multiplexer setup and hold times with respect
to the S/H input can be determined by these two equations:
t
MS (wrt S/H)
= t
MS
t
EOC (min)
= 50 60 = 10 ns
t
MH (wrt S/H)
= t
MH
+ t
EOC (max)
= 50 + 125 = 175 ns
Note that t
is a negative number; this indicates that
the data on S0 must become valid within 10 ns after S/H
goes low in order to meet the setup time requirements. S0
must be valid for a length of
(t
MH
+ t
EOC (max)
) (t
MS
t
EOC (min)
) = 185 ns.
Table 1 shows how the input channels are assigned:
TABLE 1. ADC12662 Input
Multiplexer Programming
S0
0
1
Channel
V
IN1
V
IN2
The output of the multiplexer is available to the user via the
MUX OUT pin. This output allows the user to perform addi-
tional signal processing, such as filtering or gain, before the
signal is returned to the ADC IN input and digitized. If no
additional signal processing is required, the MUX OUT pin
should be tied directly to the ADC IN pin.
See Section 9.0 (APPLICATIONS) for a simple circuit that
will alternate between the two inputs while converting at full
speed.
4.0 REFERENCE INPUTS
In addition to the fully differential V
and V
reference
inputs used on most National Semiconductor ADCs, the
ADC12662 has two sense outputs for precision control of the
ladder voltage. These sense inputs compensate for errors
due to IR drops between the reference source and the ladder
itself. The resistance of the reference ladder is typically
750
. The parasitic resistance (R
P
) of the package leads,
bond wires, PCB traces, etc. can easily be 0.5
to 1.0
or
more. This may not be significant at 8-bit or 10-bit resolu-
tions, but at 12 bits it can introduce voltage drops causing
offset and gain errors as large as 6 LSBs.
The ADC12662 provides a means to eliminate this error by
bringing out two additional pins that sense the exact voltage
at the top and bottom of the ladder. With the addition of two
op amps, the voltages on these internal nodes can be forced
to the exact value desired, as shown in Figure 10
01187621
FIGURE 9. Input Protection
A
www.national.com
16
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