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參數(shù)資料
| 型號： | ADC12662 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 12位，1.5兆赫，200毫瓦的A / D輸入多路復(fù)用器和轉(zhuǎn)換器采樣/保持 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 495K |
| 代理商： | ADC12662 |
Functional Description
The ADC12662 performs a 12-bit analog-to-digital conver-
sion using a 3 step flash technique. The first flash deter-
mines the six most significant bits, the second flash gener-
ates four more bits, and the final flash resolves the two least
significant bits. Figure 4shows the major functional blocks of
the converter. It consists of a 2
1
2
-bit Voltage Estimator, a
resistor ladder with two different resolution voltage spans, a
sample/hoId capacitor, a 4-bit flash converter with front end
multiplexer, a digitally corrected DAC, and a capacitive volt-
age divider. To pipeline the converter, there are two sample/
hold capacitors and 4-bit flash sections, which allows the
converter to acquire the next input sample while converting
the previous one. Only one of the flash converter pairs is
shown in Figure 4 to reduce complexity.
The resistor string near the center of the block diagram in
Figure 4generates the 6-bit and 10-bit reference voltages for
the first two conversions. Each of the 16 resistors at the
bottom of the string is equal to 1/1024 of the total string
resistance. These resistors form the
LSB Ladder
(The
weight of each resistor on the LSB ladder is actually equiva-
lent to four 12-bit LSBs. It is called the LSB ladder because
it has the highest resolution of all the ladders in the con-
verter) and have a voltage drop of 1/1024 of the total refer-
ence voltage (V
V
REF
) across each of them. The
remaining resistors form the
. It is comprised of
eight groups of eight resistors each connected in series (the
lowest MSB ladder resistor is actually the entire LSB ladder).
Each MSB Ladder section has
voltage across it. Within a given MSB ladder section, each of
the eight MSB resistors has 1/64 of the total reference
voltage across it. Tap points are found between all of the
1
8
of the total reference
resistors in both the MSB and LSB ladders. The Comparator
MultipIexer can connect any of these tap points, in two
adjacent groups of eight, to the sixteen comparators shown
at the right of Figure 4 This function provides the necessary
reference voltages to the comparators during the first two
flash conversions.
The six comparators, seven-resistor string (Estimator DAC
ladder), and Estimator Decoder at the left of Figure 4 form
the Voltage Estimator. The Estimator DAC, connected be-
tween V
and V
, generates the reference voltages
for the six Voltage Estimator comparators. The comparators
perform a very low resoIution A/D conversion to obtain an
“estimate” of the input voltage. This estimate is used to
control the placement of the Comparator Multiplexer, con-
necting the appropriate MSB ladder section to the sixteen
flash comparators. A total of only 22 comparators (6 in the
01187616
FIGURE 4. Functional Block Diagram
A
www.national.com
12
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