參數(shù)資料
型號: ADC1251CMJ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
中文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24
封裝: CERAMIC, DIP-24
文件頁數(shù): 5/16頁
文件大小: 301K
代理商: ADC1251CMJ
Electrical Characteristics
(Continued)
Note 6:
Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than
50 mV. This means that if AV
CC
and DV
CC
are minimum (4.75 V
DC
) and V
is maximum (
b
4.75 V
DC
), the analog input full-scale voltage must be
s g
4.8 V
DC
.
TL/H/11024–4
Note 7:
A diode exists between AV
CC
and DV
CC
as shown below.
TL/H/11024–5
To guarantee accuracy, it is required that the AV
CC
and DV
CC
be connected together to a power supply with separate bypass filters at each V
CC
pin.
Note
8:
Accuracy is guaranteed at f
CLK
e
3.5 MHz. At higher or lower clock frequencies accuracy may degrade. See the Typical Performance Characteristics
curves.
9:
Typicals are at T
J
e
25
§
C and represent most likely parametric norm.
Note 10:
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note
Note 11:
Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See Figures 1b and 1c).
Note 12:
The ADC1251’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
result in a repeatability uncertainty of
g
0.20 LSB.
Note 13:
If T
A
changes then an Auto-Zero or Auto-Cal cycle will have to be re-started. See the typical performance characteristic curves.
Note 14:
After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15:
When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
end of the interval t
A
, therefore making t
A
end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR. If the falling edge of the clock
is synchronous to the rising edge of WR then t
A
will end exactly 6.5 clock periods after the rising edge of WR. This does not occur when S/H control is used.
Note 16:
The CAL line must be high before a conversion is started.
Note 17:
The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18:
The ADC1251 reference ladder is composed solely of capacitors.
Note 19:
A Military RETS Electrical Test Specification is available on request. At time of printing the ADC1251CMJ/883 RETS specification complies fully with the
boldface
limits in this column.
TL/H/11024–6
FIGURE 1a. Transfer Characteristic
5
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