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參數(shù)資料
| 型號(hào)： | ADC1251BIJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 301K |
| 代理商： | ADC1251BIJ |
AC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e a
5.0V, V
b
e b
5.0V, t
r
e
t
f
e
20 ns unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
;
all other limits T
A
e
T
J
e
25
§
C. (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limit
Units
(Limit)
(Notes 10, 19)
f
CLK
Clock Frequency
MHz
0.5
6.0
MHz(min)
MHz(max)
3.5
Clock Duty Cycle
50
%
40
60
%(min)
%(max)
t
C
Conversion Time Using WR
to Start a Conversion
27(1/f
CLK
)
27(1/f
CLK
)
a
250 ns
(max)
f
CLK
e
3.5 MHz, AZ
e
‘‘1’’
7.7
7.95
m
s(max)
f
CLK
e
1.75 MHz, AZ
e
‘‘0’’
15.4
15.65
m
s(max)
t
C
Conversion Time Using S/H
to Start a Conversion
AZ
e
‘‘1’’
34(1/f
CLK
)
34(1/f
CLK
)
a
250 ns
(max)
f
CLK
e
3.5 MHz, AZ
e
‘‘1’’
9.7
9.95
m
s(max)
t
A
Acquisition Time (Note 15)
R
SOURCE
e
50
X
3.5
3.5
m
s(min)
t
IA
Internal Acquisition Time
(When Using WR Control Only)
7(1/f
CLK
)
7(1/f
CLK
)
(max)
t
ZA
Auto Zero Time
a
Acquisition Time
33(1/f
CLK
)
33(1/f
CLK
)
a
250 ns
(max)
f
CLK
e
1.75 MHz
18.8
19.05
m
s(max)
t
D(EOC)L
Delay from Hold Command
to Falling Edge of EOC
Using WR Control
200
350
ns(max)
Using S/H Control
100
150
ns(max)
t
CAL
Calibration Time
1399(1/f
CLK
)
1399 (1/f
CLK
)
(max)
f
CLK
e
3.5 MHz
399
400
m
s(max)
t
W(CAL)L
Calibration Pulse Width
(Note 16)
60
200
ns(min)
t
W(WR)L
Minimum WR Pulse Width
60
200
ns(min)
t
ACC
Maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)
C
L
e
100 pF
50
95
ns(max)
t
0H
, t
1H
TRI-STATE Control
(Delay from Rising Edge of
RD to Hi-Z State)
R
L
e
1 k
X
, C
L
e
100 pF
30
70
ns(max)
t
PD(INT)
Maximum Delay from Falling Edge
of RD or WR to Reset of INT
100
175
ns(max)
t
RR
Delay between Successive RD Pulses
30
60
ns(min)
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
V
b
or V
IN
l
(AV
CC
or DV
CC
), the current at that pin should be limited to
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.
Note 4:
The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation
a
1 TTL Load on each digital
output). Caution should be taken not to exceed absolute maximum power rating when the device is operating in severe fault condition (ex. when any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
(maximum junction
temperature),
i
JA
(package junction to ambient thermal resistance), and T
A
(ambient temperature). The maximum allowable power dissipation at any temperature
is P
Dmax
e
(T
Jmax
b
T
A
)/
i
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
e
150
§
C, and the typical thermal
resistance (
i
JA
) of the ADC1251 with CMJ, BIJ, and CIJ suffixes when board mounted is 51
§
C/W.
Note 5:
Human body model, 100 pF discharged through a 1.5 k
X
resistor.
4
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