參數(shù)資料
型號(hào): ADC124S021CIMMX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 4 Channel, 200 kSPS, 12-Bit A/D Converter
中文描述: 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10
封裝: MSOP-10
文件頁(yè)數(shù): 16/19頁(yè)
文件大?。?/td> 909K
代理商: ADC124S021CIMMX
Applications Information
(Continued)
conversion, it is necessary to clock in the data indicating the
input that is selected for the conversion after the current one.
See Tables 1, 2 and 3.
If CS and SCLK go low simultaneously, it is the following
rising edge of SCLK that is considered the first rising edge
for clocking data into DIN.
There are no power-up delays or dummy conversions re-
quired with the ADC124S021. The ADC is able to sample
and convert an input to full conversion immediately following
power up. The first conversion result after power-up will be
that of IN1.
TABLE 1. Control Register Bits
Bit 7 (MSB)
DONTC
Bit 6
DONTC
Bit 5
ADD2
Bit 4
ADD1
Bit 3
ADD0
Bit 2
DONTC
Bit 1
DONTC
Bit 0
DONTC
TABLE 2. Control Register Bit Descriptions
Bit #:
7 - 6, 2 - 0
5
4
3
Symbol:
DONTC
ADD2
ADD1
ADD0
Description
Don’t care. The value of these bits do not affect device operation.
These three bits determine which input channel will be sampled and
converted in the next track/hold cycle. The mapping between codes and
channels is shown in
Table 3
.
TABLE 3. Input Channel Selection
ADD2
x
x
x
x
ADD1
0
0
1
1
ADD0
0
1
0
1
Input Channel
IN1 (Default)
IN2
IN3
IN4
A
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