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參數(shù)資料
| 型號： | ADC12181EVAL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter |
| 中文描述： | 12位，5兆赫自校準，流水線A / D轉換器 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 322K |
| 代理商： | ADC12181EVAL |
Specification Definitions
APERTURE JITTER
is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY
See Sampling Delay.
CLOCK DUTY CYCLE
is the ratio of the time that the clock
waveform is high to the total time for one clock cycle.
DIFFERENTIAL NON-LINEARITY (DNL)
is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS)
is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD -
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH
is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
FULL SCALE ERROR
is the difference between the input
voltage just causing a transition to positive full scale and
V
REF
-1.5 LSB.
INTEGRAL NON-LINEARITY (INL)
is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
1
2
LSB below the first code transition)
through positive full scale (1
1
2
LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value. The end
point test method is used. INL is commonly measured at
rated clock frequency with a ramp input.
INTERMODULATION DISTORTION (IMD)
is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to theADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dB.
PIPELINE DELAY (LATENCY)
is the number of clock cycles
between initiation of conversion and the availability of that
conversion result at the output. New data is available at
every clock cycle, but the data lags the conversion by the
pipeline delay plus the Output Delay.
SAMPLING (APERTURE) DELAY
is the time after the edge
of the clock to when the input signal is acquired or held for
conversion.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SI-
NAD)
is the ratio expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral
components below half the clock frequency, including har-
monics but excluding dc.
SIGNAL TO NOISE RATIO (SNR)
is the ratio of the rms
value of the input signal to the rms value of the other spectral
components below one-half the sampling frequency, not in-
cluding harmonics or dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD)
is the ratio of the
rms total of the first six harmonic components, to the rms
value of the input signal.
ZERO SCALE OFFSET ERROR
is the difference between
the ideal input voltage (
1
2
LSB) and the actual input voltage
that causes a transition from an output code of zero to an
output code of one.
ZERO ERROR
See Zero Scale Offset Error.
A
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| ADC121C021CIMK/NOPB | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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