參數(shù)資料
型號： ADC1213D105HN
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Dual 12-bit ADC; 105 Msps
封裝： ADC1213D105HN/C1<SOT684-7 (HVQFN56)|<<http://www.nxp.com/packages/SOT684-7.html<1<Always Pb-free,;ADC1213D105HN/C1<SOT684-7 (HVQFN56)|<<http://www.nxp.com/packages/SOT684
文件頁數(shù)： 28/42頁
文件大小： 632K
代理商： ADC1213D105HN
ADC1213D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 9 June 2011
34 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Table 47.
Cfg_02_2_LID (address 082Dh)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
000
not used
4 to 0
LID[4:0]
R/W
11100
defines lane 1 identification number
Table 48.
Cfg01_13_FCHK (address 084Ch)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FCHK[7:0]
R
00000000 defines the checksum value for lane 0
checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
Table 49.
Cfg02_13_FCHK (address 084Dh)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FCHK[7:0]
R
00000000 defines the checksum value for lane 1
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Table 50.
Lane0_0_Ctrl (address 0870h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
0
not used
6
SCR_IN_MODE
R/W
defines the input type for scrambler and 8-bit/10-bit units:
0 (reset)
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
1
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_Ctrl register)
5 to 4
LANE_MODE[1:0]
R/W
defines output type of lane output unit:
00 (reset)
normal mode: lane output is the 8-bit/10-bit output unit
01
constant mode: lane output is set to a constant (0
0)
10
toggle mode: lane output is toggling between 0
0 and 0 1
11
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
3
-
0
not used
2
LANE_POL
R/W
defines lane polarity:
0
lane polarity is normal
1
lane polarity is inverted
1
LANE_CLK_POS_EDGE R/W
defines lane clock polarity:
0
lane clock provided to the serializer is active on positive
edge
1
lane clock provided to the serializer is active on negative edge
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADC1213D105HN/C1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
ADC1213D105HN/C1,5 功能描述:模數(shù)轉(zhuǎn)換器 - ADC DUAL 12b ADC 105MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADC1213D105HN/C1/5 功能描述:模數(shù)轉(zhuǎn)換器 - ADC DUAL 12b ADC 105MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADC1213D105HN-C1 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Bulk
ADC1213D105HN-C18 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Tape and Reel
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