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參數(shù)資料
| 型號： | ADC12081CIVT |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 352K |
| 代理商： | ADC12081CIVT |
Applications Information
(Continued)
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected be-
tween the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 6gives an example of a suitable layout.All analog cir-
cuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
All ground connections should have a low inductance path to
ground.
6.0 Layout and Grounding
The ADC12081 can achieve impressive dynamic perfor-
mance. To achieve the best dynamic performance with the
ADC12081, the clock source driving the CLK input must be
free of jitter. For best ac performance, isolating the ADC
clock from any digital circuitry should be done with adequate
buffers, as with a clock tree. See Figure 7
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce phase noise (jitter) into the clock
signal, which can lead to increased distortion. Even lines
with 90 crossings have capacitive coupling, so try to avoid
even these 90 crossings of the clock line.
7.0 Common Application Pitfalls
Driving the inputs (analog or digital) beyond the power
supply rails.
For proper operation, all inputs should not go
more than 300mV beyond the supply rails (more than
DS100150-24
FIGURE 6. Layout example
DS100150-25
FIGURE 7. Isolating the ADC clock from other circuitry
with a clock tree.
A
www.national.com
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC12081CIVT/NOPB | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12081CIVTX | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12081CIVTX NOPB | 制造商:National Semiconductor 功能描述:ADC Single Pipelined 5Msps 12-bit Parallel 32-Pin LQFP T/R |
| ADC12081CIVTX/NOPB | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12081EVAL | 功能描述:BOARD EVALUATION FOR ADC12081 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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