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參數(shù)資料
| 型號： | ADC12062CIVF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 1 MHz, 75 mW A/D Converter |
| 中文描述： | 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 355K |
| 代理商： | ADC12062CIVF |
AC Electrical Characteristics
V
REF
a
(SENSE)
e a
4.096V, V
REF
b
(SENSE)
e
AGND, and f
s
e
1 MHz, unless otherwise specified.
Boldface limits apply
for T
A
e
T
J
from T
MIN
to T
MAX
;
all other limits T
A
e
T
J
e a
25
§
C.
The following specifications apply for DV
CC
e
AV
CC
e
a
5V,
Symbol
Parameter
Conditions
Typ
Limit
(Note 8)
Units
(Limits)
(Note 7)
f
s
Maximum Sampling Rate
(1/t
THROUGHPUT
)
1
MHz (min)
t
CONV
Conversion Time
(S/H Low to EOC High)
740
600
980
ns (min)
ns (max)
t
AD
Aperture Delay
(S/H Low to Input Voltage Held)
20
ns
t
S/H
S/H Pulse Width
5
ns (min)
ns (max)
550
t
EOC
S/H Low to EOC Low
95
60
125
ns (min)
ns (max)
t
ACC
Access Time
(RD Low or OE High to Data Valid)
C
L
e
100 pF
10
20
ns (max)
t
1H
, t
0H
TRI-STATE Control
(RD High or OE Low to Databus TRI-STATE)
R
L
e
1k, C
L
e
10 pF
25
40
ns (max)
t
INTH
Delay from RD Low to INT High
C
L
e
100 pF
35
60
ns (max)
t
INTL
Delay from EOC High to INT Low
C
L
e
100 pF
b
25
b
35
b
10
ns (min)
ns (max)
t
UPDATE
EOC High to New Data Valid
5
15
ns (max)
t
MS
Multiplexer Address Setup Time
(MUX Address Valid to EOC Low)
50
ns (min)
t
MH
Multiplexer Address Hold Time
(EOC Low to MUX Address Invalid)
50
ns (min)
t
CSS
CS Setup Time
(CS Low to RD Low, S/H Low, or OE High)
20
ns (min)
t
CSH
CS Hold Time
(CS High after RD High, S/H High, or OE Low)
20
ns (min)
t
WU
Wake-Up Time
(PD High to First S/H Low)
1
m
s
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteris-
tics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions.
Note 2:
All voltages are measured with respect to GND (GND
e
AGND
e
DGND), unless otherwise specified.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
GND or V
IN
l
V
CC
) the absolute value of current at that pin should be
limited to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
i
JA
and the ambient temperature T
A
. The maximum
allowable power dissipation at any temperature is P
D
e
(T
JMAX
b
T
A
)/
i
JA
or the number given in the Absolute Maximum Ratings, whichever is lower.
i
JA
for the V
(PLCC) package is 55
§
C/W.
i
JA
for the VF (PQFP) package is 62
§
C/W. In most cases the maximum derated power dissipation will be reached only during fault
conditions.
4
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