參數(shù)資料
型號(hào)： ADC12048EVAL
廠商： National Semiconductor Corporation
英文描述： 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter
中文描述： 12位帶符號(hào)216 kHz的8聲道采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 635K
代理商： ADC12048EVAL
Digital Logic Input/Output Characteristics
The following specifications apply to the ADC12048 for V
+ = V
+ = 5V, V
+ = 4.096V, V
= 0.0V, 12-bit + sign con-
version mode, f
= 12.0 MHz, R
= 25
, source impedance for V
+ and V
≤
1
, fully differential input with fixed
2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
2.0
0.8
2.0
2.0
Unit
(Limit)
V (min)
V (max)
μA (max)
μA (max)
V
IH
V
IL
I
IH
I
IL
V
OH
Logic High Input Voltage
Logic Low Input Voltage
Logic High Input Current
Logic Low Input Current
Logic High Output Voltage
V
A
+ = V
D
+ = 5.5V
V
A
+ = V
D
+ = 4.5V
V
IN
= 5V
V
IN
= 0V
V
A
+ = V
D
+ = 4.5V
I
OUT
= 1.6 mA
V
A
+ = V
D
+ = 4.5V
I
OUT
= 1.6 mA
V
OUT
= 0V
V
OUT
= 5V
0.035
0.035
2.4
V (min)
V
OL
Logic Low Output Voltage
0.4
V (max)
I
OFF
TRI-STATE
Output
Leakage Current
D12–D0 Input
Capacitance
±
2.0
μA (max)
C
IN
10
pF
Converter AC Characteristics
The following specifications apply to the ADC12048 for V
+ = V
+ = 5V, V
+ = 4.096V, V
= 0.0V, 12-bit + sign con-
version mode, f
= 12.0 MHz, R
= 25
, source impedance for V
+ and V
≤
1
, fully differential input with fixed
2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
Boldface limits apply for T
A
=
T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C
Symbol
Parameter
Conditions
Typical
(Note 10)
78
4946
50
Limits
(Note 11)
78 clks + 120 ns
4946 clks + 120 ns
Unit
(Limit)
clks (max)
clks (max)
%
% (min)
% (max)
clks (max)
clks (max)
clks (max)
t
Z
t
CAL
Auto Zero Time
Full Calibration Time
CLK Duty Cycle
40
60
44
t
CONV
t
AcqSYNCOUT
Conversion Time
Acquisition Time
(Programmable)
Sync-Out Mode
Minimum for 13 Bits
Maximum for 13 Bits
44
9
79
9 clks + 120 ns
79 clks + 120 ns
Digital Timing Characteristics
The following specifications apply to the ADC12048, 13-bit data bus width, V
A
+ = V
D
+ = 5V, f
CLK
= 12 MHz, t
f
= 3 ns and C
L
= 50 pF on data I/O lines
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
t
TPR
Throughput Rate
Sync-Out Mode (SYNC Bit
= “0”) 9 Clock Cycles of
Acquisition Time
222
kHz
t
CSWR
t
WRCS
t
WR
t
WRSETFalling
t
WRHOLDFalling
Write Hold Time
t
WRSETRising
Write Setup Time
t
WRHOLDRising
Write Hold Time
t
CSRD
Falling Edge of CS to Falling Edge of RD
t
RDCS
Rising Edge of RD to Rising Edge of CS
t
RDDATA
Falling Edge of RD to Valid Data
Falling Edge of CS to Falling Edge of WR
Active Edge of WR to Rising Edge of CS
WR Pulse Width
Write Setup Time
0
0
20
ns
ns
30
20
5
20
5
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns
ns
ns (max)
WMODE = “1”
WMODE = “1”
WMODE = “0”
WMODE = “0”
0
0
8-Bit Mode (BW Bit = “0”)
40
58
A
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